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lanttu |
-------------------------------------------------------------------------------
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-- Title : Ring network, max 16 agents. Number of busses determined by
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-- n_ag_g will be used, starting from port0. Currently only
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-- even-sized rings will be allowed.
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-- Project :
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-------------------------------------------------------------------------------
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-- File : ring_network_max16ag.vhd
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-- Author : Antti Alhonen
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-- Company :
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-- Last update: 2011-08-26
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-- Platform :
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009/08/07 1.0 alhonena Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity ring_network_max16ag is
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generic (
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n_ag_g : integer := 16;
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stfwd_en_g : integer := 0;
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diag_en_g : integer := 0;
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data_width_g : integer := 32;
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addr_width_g : integer := 32;
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packet_length_g : integer := 6;
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tx_len_width_g : integer := 16;
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timeout_g : integer := 5;
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fill_packet_g : integer := 0;
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lut_en_g : integer := 0;
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len_flit_en_g : integer := 1;
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oaddr_flit_en_g : integer := 0;
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status_en_g : integer := 0;
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fifo_depth_g : integer := 6;
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ring_freq_g : integer := 50000000;
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ip_freq_g : integer := 50000000);
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port (
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clk_net : in std_logic;
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clk_ip : in std_logic;
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rst_n : in std_logic;
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port0_tx_av_in : in std_logic;
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port0_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port0_tx_we_in : in std_logic;
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port0_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port0_tx_full_out : out std_logic;
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port0_rx_av_out : out std_logic;
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port0_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port0_rx_re_in : in std_logic;
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port0_rx_empty_out : out std_logic;
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port1_tx_av_in : in std_logic;
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port1_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port1_tx_we_in : in std_logic;
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port1_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port1_tx_full_out : out std_logic;
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port1_rx_av_out : out std_logic;
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port1_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port1_rx_re_in : in std_logic;
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port1_rx_empty_out : out std_logic;
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port2_tx_av_in : in std_logic;
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port2_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port2_tx_we_in : in std_logic;
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port2_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port2_tx_full_out : out std_logic;
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port2_rx_av_out : out std_logic;
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port2_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port2_rx_re_in : in std_logic;
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port2_rx_empty_out : out std_logic;
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port3_tx_av_in : in std_logic;
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port3_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port3_tx_we_in : in std_logic;
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port3_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port3_tx_full_out : out std_logic;
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port3_rx_av_out : out std_logic;
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port3_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port3_rx_re_in : in std_logic;
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port3_rx_empty_out : out std_logic;
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port4_tx_av_in : in std_logic;
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port4_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port4_tx_we_in : in std_logic;
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port4_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port4_tx_full_out : out std_logic;
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port4_rx_av_out : out std_logic;
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port4_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port4_rx_re_in : in std_logic;
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port4_rx_empty_out : out std_logic;
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port5_tx_av_in : in std_logic;
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port5_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port5_tx_we_in : in std_logic;
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port5_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port5_tx_full_out : out std_logic;
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port5_rx_av_out : out std_logic;
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port5_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port5_rx_re_in : in std_logic;
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port5_rx_empty_out : out std_logic;
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port6_tx_av_in : in std_logic;
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port6_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port6_tx_we_in : in std_logic;
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port6_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port6_tx_full_out : out std_logic;
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port6_rx_av_out : out std_logic;
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port6_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port6_rx_re_in : in std_logic;
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port6_rx_empty_out : out std_logic;
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port7_tx_av_in : in std_logic;
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port7_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port7_tx_we_in : in std_logic;
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port7_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port7_tx_full_out : out std_logic;
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port7_rx_av_out : out std_logic;
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port7_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port7_rx_re_in : in std_logic;
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port7_rx_empty_out : out std_logic;
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port8_tx_av_in : in std_logic;
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port8_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port8_tx_we_in : in std_logic;
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port8_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port8_tx_full_out : out std_logic;
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port8_rx_av_out : out std_logic;
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port8_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port8_rx_re_in : in std_logic;
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port8_rx_empty_out : out std_logic;
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port9_tx_av_in : in std_logic;
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port9_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port9_tx_we_in : in std_logic;
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port9_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port9_tx_full_out : out std_logic;
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port9_rx_av_out : out std_logic;
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port9_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port9_rx_re_in : in std_logic;
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port9_rx_empty_out : out std_logic;
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port10_tx_av_in : in std_logic;
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port10_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port10_tx_we_in : in std_logic;
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port10_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port10_tx_full_out : out std_logic;
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port10_rx_av_out : out std_logic;
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port10_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port10_rx_re_in : in std_logic;
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port10_rx_empty_out : out std_logic;
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port11_tx_av_in : in std_logic;
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port11_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port11_tx_we_in : in std_logic;
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port11_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port11_tx_full_out : out std_logic;
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port11_rx_av_out : out std_logic;
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port11_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port11_rx_re_in : in std_logic;
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port11_rx_empty_out : out std_logic;
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port12_tx_av_in : in std_logic;
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port12_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port12_tx_we_in : in std_logic;
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port12_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port12_tx_full_out : out std_logic;
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port12_rx_av_out : out std_logic;
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port12_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port12_rx_re_in : in std_logic;
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port12_rx_empty_out : out std_logic;
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port13_tx_av_in : in std_logic;
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port13_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port13_tx_we_in : in std_logic;
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port13_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port13_tx_full_out : out std_logic;
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port13_rx_av_out : out std_logic;
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port13_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port13_rx_re_in : in std_logic;
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port13_rx_empty_out : out std_logic;
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port14_tx_av_in : in std_logic;
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port14_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port14_tx_we_in : in std_logic;
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port14_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port14_tx_full_out : out std_logic;
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port14_rx_av_out : out std_logic;
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port14_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port14_rx_re_in : in std_logic;
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port14_rx_empty_out : out std_logic;
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port15_tx_av_in : in std_logic;
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port15_tx_data_in : in std_logic_vector (data_width_g -1 downto 0);
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port15_tx_we_in : in std_logic;
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port15_tx_txlen_in : in std_logic_vector (tx_len_width_g -1 downto 0);
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port15_tx_full_out : out std_logic;
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port15_rx_av_out : out std_logic;
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port15_rx_data_out : out std_logic_vector (data_width_g -1 downto 0);
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port15_rx_re_in : in std_logic;
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port15_rx_empty_out : out std_logic
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);
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end ring_network_max16ag;
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architecture structural of ring_network_max16ag is
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component ring_with_pkt_codec_top
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generic (
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n_ag_g : integer;
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stfwd_en_g : integer;
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diag_en_g : integer;
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data_width_g : integer;
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addr_width_g : integer;
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packet_length_g : integer;
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tx_len_width_g : integer;
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timeout_g : integer;
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fill_packet_g : integer;
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lut_en_g : integer;
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len_flit_en_g : integer;
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oaddr_flit_en_g : integer;
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status_en_g : integer;
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fifo_depth_g : integer;
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ring_freq_g : integer;
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ip_freq_g : integer);
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port (
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clk_net : in std_logic;
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clk_ip : in std_logic;
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rst_n : in std_logic;
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tx_av_in : in std_logic_vector (n_ag_g-1 downto 0);
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tx_data_in : in std_logic_vector (n_ag_g * data_width_g -1 downto 0);
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tx_we_in : in std_logic_vector (n_ag_g-1 downto 0);
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tx_txlen_in : in std_logic_vector (n_ag_g * tx_len_width_g -1 downto 0);
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tx_full_out : out std_logic_vector (n_ag_g-1 downto 0);
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tx_empty_out : out std_logic_vector (n_ag_g-1 downto 0);
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rx_av_out : out std_logic_vector (n_ag_g-1 downto 0);
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rx_data_out : out std_logic_vector (n_ag_g * data_width_g -1 downto 0);
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rx_re_in : in std_logic_vector (n_ag_g-1 downto 0);
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rx_empty_out : out std_logic_vector (n_ag_g-1 downto 0));
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end component;
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signal tx_av_in_comp : std_logic_vector (n_ag_g-1 downto 0);
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signal tx_data_in_comp : std_logic_vector (n_ag_g * data_width_g -1 downto 0);
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signal tx_we_in_comp : std_logic_vector (n_ag_g-1 downto 0);
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signal tx_txlen_in_comp : std_logic_vector (n_ag_g * tx_len_width_g -1 downto 0);
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signal tx_full_out_comp : std_logic_vector (n_ag_g-1 downto 0);
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signal rx_av_out_comp : std_logic_vector (n_ag_g-1 downto 0);
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signal rx_data_out_comp : std_logic_vector (n_ag_g * data_width_g -1 downto 0);
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signal rx_re_in_comp : std_logic_vector (n_ag_g-1 downto 0);
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signal rx_empty_out_comp : std_logic_vector (n_ag_g-1 downto 0);
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begin -- structural
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assert n_ag_g mod 2 = 0 report "Only even-sized rings currently supported." severity failure;
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assert n_ag_g < 17 report "This ring network supports up to 16 agents." severity failure;
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ag0 : if n_ag_g > 0 generate
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tx_av_in_comp(0) <= port0_tx_av_in;
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tx_data_in_comp(data_width_g-1 downto 0) <= port0_tx_data_in;
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tx_we_in_comp(0) <= port0_tx_we_in;
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tx_txlen_in_comp(tx_len_width_g-1 downto 0) <= port0_tx_txlen_in;
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rx_re_in_comp(0) <= port0_rx_re_in;
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port0_tx_full_out <= tx_full_out_comp(0);
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port0_rx_av_out <= rx_av_out_comp(0);
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port0_rx_data_out <= rx_data_out_comp(data_width_g-1 downto 0);
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port0_rx_empty_out <= rx_empty_out_comp(0);
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end generate ag0;
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ag1 : if n_ag_g > 1 generate
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tx_av_in_comp(1) <= port1_tx_av_in;
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tx_data_in_comp(2*data_width_g-1 downto data_width_g) <= port1_tx_data_in;
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|
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tx_we_in_comp(1) <= port1_tx_we_in;
|
277 |
|
|
tx_txlen_in_comp(2*tx_len_width_g-1 downto tx_len_width_g) <= port1_tx_txlen_in;
|
278 |
|
|
rx_re_in_comp(1) <= port1_rx_re_in;
|
279 |
|
|
|
280 |
|
|
port1_tx_full_out <= tx_full_out_comp(1);
|
281 |
|
|
port1_rx_av_out <= rx_av_out_comp(1);
|
282 |
|
|
port1_rx_data_out <= rx_data_out_comp(2*data_width_g-1 downto data_width_g);
|
283 |
|
|
port1_rx_empty_out <= rx_empty_out_comp(1);
|
284 |
|
|
end generate ag1;
|
285 |
|
|
|
286 |
|
|
ag2 : if n_ag_g > 2 generate
|
287 |
|
|
tx_av_in_comp(2) <= port2_tx_av_in;
|
288 |
|
|
tx_data_in_comp(3*data_width_g-1 downto 2*data_width_g) <= port2_tx_data_in;
|
289 |
|
|
tx_we_in_comp(2) <= port2_tx_we_in;
|
290 |
|
|
tx_txlen_in_comp(3*tx_len_width_g-1 downto 2*tx_len_width_g) <= port2_tx_txlen_in;
|
291 |
|
|
rx_re_in_comp(2) <= port2_rx_re_in;
|
292 |
|
|
|
293 |
|
|
port2_tx_full_out <= tx_full_out_comp(2);
|
294 |
|
|
port2_rx_av_out <= rx_av_out_comp(2);
|
295 |
|
|
port2_rx_data_out <= rx_data_out_comp(3*data_width_g-1 downto 2*data_width_g);
|
296 |
|
|
port2_rx_empty_out <= rx_empty_out_comp(2);
|
297 |
|
|
end generate ag2;
|
298 |
|
|
|
299 |
|
|
ag3 : if n_ag_g > 3 generate
|
300 |
|
|
tx_av_in_comp(3) <= port3_tx_av_in;
|
301 |
|
|
tx_data_in_comp(4*data_width_g-1 downto 3*data_width_g) <= port3_tx_data_in;
|
302 |
|
|
tx_we_in_comp(3) <= port3_tx_we_in;
|
303 |
|
|
tx_txlen_in_comp(4*tx_len_width_g-1 downto 3*tx_len_width_g) <= port3_tx_txlen_in;
|
304 |
|
|
rx_re_in_comp(3) <= port3_rx_re_in;
|
305 |
|
|
|
306 |
|
|
port3_tx_full_out <= tx_full_out_comp(3);
|
307 |
|
|
port3_rx_av_out <= rx_av_out_comp(3);
|
308 |
|
|
port3_rx_data_out <= rx_data_out_comp(4*data_width_g-1 downto 3*data_width_g);
|
309 |
|
|
port3_rx_empty_out <= rx_empty_out_comp(3);
|
310 |
|
|
end generate ag3;
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
ag4 : if n_ag_g > 4 generate
|
315 |
|
|
tx_av_in_comp(4) <= port4_tx_av_in;
|
316 |
|
|
tx_data_in_comp(5*data_width_g-1 downto 4*data_width_g) <= port4_tx_data_in;
|
317 |
|
|
tx_we_in_comp(4) <= port4_tx_we_in;
|
318 |
|
|
tx_txlen_in_comp(5*tx_len_width_g-1 downto 4*tx_len_width_g) <= port4_tx_txlen_in;
|
319 |
|
|
rx_re_in_comp(4) <= port4_rx_re_in;
|
320 |
|
|
|
321 |
|
|
port4_tx_full_out <= tx_full_out_comp(4);
|
322 |
|
|
port4_rx_av_out <= rx_av_out_comp(4);
|
323 |
|
|
port4_rx_data_out <= rx_data_out_comp(5*data_width_g-1 downto 4*data_width_g);
|
324 |
|
|
port4_rx_empty_out <= rx_empty_out_comp(4);
|
325 |
|
|
end generate ag4;
|
326 |
|
|
|
327 |
|
|
ag5 : if n_ag_g > 5 generate
|
328 |
|
|
tx_av_in_comp(5) <= port5_tx_av_in;
|
329 |
|
|
tx_data_in_comp(6*data_width_g-1 downto 5*data_width_g) <= port5_tx_data_in;
|
330 |
|
|
tx_we_in_comp(5) <= port5_tx_we_in;
|
331 |
|
|
tx_txlen_in_comp(6*tx_len_width_g-1 downto 5*tx_len_width_g) <= port5_tx_txlen_in;
|
332 |
|
|
rx_re_in_comp(5) <= port5_rx_re_in;
|
333 |
|
|
|
334 |
|
|
port5_tx_full_out <= tx_full_out_comp(5);
|
335 |
|
|
port5_rx_av_out <= rx_av_out_comp(5);
|
336 |
|
|
port5_rx_data_out <= rx_data_out_comp(6*data_width_g-1 downto 5*data_width_g);
|
337 |
|
|
port5_rx_empty_out <= rx_empty_out_comp(5);
|
338 |
|
|
end generate ag5;
|
339 |
|
|
|
340 |
|
|
ag6 : if n_ag_g > 6 generate
|
341 |
|
|
tx_av_in_comp(6) <= port6_tx_av_in;
|
342 |
|
|
tx_data_in_comp(7*data_width_g-1 downto 6*data_width_g) <= port6_tx_data_in;
|
343 |
|
|
tx_we_in_comp(6) <= port6_tx_we_in;
|
344 |
|
|
tx_txlen_in_comp(7*tx_len_width_g-1 downto 6*tx_len_width_g) <= port6_tx_txlen_in;
|
345 |
|
|
rx_re_in_comp(6) <= port6_rx_re_in;
|
346 |
|
|
|
347 |
|
|
port6_tx_full_out <= tx_full_out_comp(6);
|
348 |
|
|
port6_rx_av_out <= rx_av_out_comp(6);
|
349 |
|
|
port6_rx_data_out <= rx_data_out_comp(7*data_width_g-1 downto 6*data_width_g);
|
350 |
|
|
port6_rx_empty_out <= rx_empty_out_comp(6);
|
351 |
|
|
end generate ag6;
|
352 |
|
|
|
353 |
|
|
ag7 : if n_ag_g > 7 generate
|
354 |
|
|
tx_av_in_comp(7) <= port7_tx_av_in;
|
355 |
|
|
tx_data_in_comp(8*data_width_g-1 downto 7*data_width_g) <= port7_tx_data_in;
|
356 |
|
|
tx_we_in_comp(7) <= port7_tx_we_in;
|
357 |
|
|
tx_txlen_in_comp(8*tx_len_width_g-1 downto 7*tx_len_width_g) <= port7_tx_txlen_in;
|
358 |
|
|
rx_re_in_comp(7) <= port7_rx_re_in;
|
359 |
|
|
|
360 |
|
|
port7_tx_full_out <= tx_full_out_comp(7);
|
361 |
|
|
port7_rx_av_out <= rx_av_out_comp(7);
|
362 |
|
|
port7_rx_data_out <= rx_data_out_comp(8*data_width_g-1 downto 7*data_width_g);
|
363 |
|
|
port7_rx_empty_out <= rx_empty_out_comp(7);
|
364 |
|
|
end generate ag7;
|
365 |
|
|
|
366 |
|
|
ag8 : if n_ag_g > 8 generate
|
367 |
|
|
tx_av_in_comp(8) <= port8_tx_av_in;
|
368 |
|
|
tx_data_in_comp(9*data_width_g-1 downto 8*data_width_g) <= port8_tx_data_in;
|
369 |
|
|
tx_we_in_comp(8) <= port8_tx_we_in;
|
370 |
|
|
tx_txlen_in_comp(9*tx_len_width_g-1 downto 8*tx_len_width_g) <= port8_tx_txlen_in;
|
371 |
|
|
rx_re_in_comp(8) <= port8_rx_re_in;
|
372 |
|
|
|
373 |
|
|
port8_tx_full_out <= tx_full_out_comp(8);
|
374 |
|
|
port8_rx_av_out <= rx_av_out_comp(8);
|
375 |
|
|
port8_rx_data_out <= rx_data_out_comp(9*data_width_g-1 downto 8*data_width_g);
|
376 |
|
|
port8_rx_empty_out <= rx_empty_out_comp(8);
|
377 |
|
|
end generate ag8;
|
378 |
|
|
|
379 |
|
|
ag9 : if n_ag_g > 9 generate
|
380 |
|
|
tx_av_in_comp(9) <= port9_tx_av_in;
|
381 |
|
|
tx_data_in_comp(10*data_width_g-1 downto 9*data_width_g) <= port9_tx_data_in;
|
382 |
|
|
tx_we_in_comp(9) <= port9_tx_we_in;
|
383 |
|
|
tx_txlen_in_comp(10*tx_len_width_g-1 downto 9*tx_len_width_g) <= port9_tx_txlen_in;
|
384 |
|
|
rx_re_in_comp(9) <= port9_rx_re_in;
|
385 |
|
|
|
386 |
|
|
port9_tx_full_out <= tx_full_out_comp(9);
|
387 |
|
|
port9_rx_av_out <= rx_av_out_comp(9);
|
388 |
|
|
port9_rx_data_out <= rx_data_out_comp(10*data_width_g-1 downto 9*data_width_g);
|
389 |
|
|
port9_rx_empty_out <= rx_empty_out_comp(9);
|
390 |
|
|
end generate ag9;
|
391 |
|
|
|
392 |
|
|
ag10 : if n_ag_g > 10 generate
|
393 |
|
|
tx_av_in_comp(10) <= port10_tx_av_in;
|
394 |
|
|
tx_data_in_comp(11*data_width_g-1 downto 10*data_width_g) <= port10_tx_data_in;
|
395 |
|
|
tx_we_in_comp(10) <= port10_tx_we_in;
|
396 |
|
|
tx_txlen_in_comp(11*tx_len_width_g-1 downto 10*tx_len_width_g) <= port10_tx_txlen_in;
|
397 |
|
|
rx_re_in_comp(10) <= port10_rx_re_in;
|
398 |
|
|
|
399 |
|
|
port10_tx_full_out <= tx_full_out_comp(10);
|
400 |
|
|
port10_rx_av_out <= rx_av_out_comp(10);
|
401 |
|
|
port10_rx_data_out <= rx_data_out_comp(11*data_width_g-1 downto 10*data_width_g);
|
402 |
|
|
port10_rx_empty_out <= rx_empty_out_comp(10);
|
403 |
|
|
end generate ag10;
|
404 |
|
|
|
405 |
|
|
ag11 : if n_ag_g > 11 generate
|
406 |
|
|
tx_av_in_comp(11) <= port11_tx_av_in;
|
407 |
|
|
tx_data_in_comp(12*data_width_g-1 downto 11*data_width_g) <= port11_tx_data_in;
|
408 |
|
|
tx_we_in_comp(11) <= port11_tx_we_in;
|
409 |
|
|
tx_txlen_in_comp(12*tx_len_width_g-1 downto 11*tx_len_width_g) <= port11_tx_txlen_in;
|
410 |
|
|
rx_re_in_comp(11) <= port11_rx_re_in;
|
411 |
|
|
|
412 |
|
|
port11_tx_full_out <= tx_full_out_comp(11);
|
413 |
|
|
port11_rx_av_out <= rx_av_out_comp(11);
|
414 |
|
|
port11_rx_data_out <= rx_data_out_comp(12*data_width_g-1 downto 11*data_width_g);
|
415 |
|
|
port11_rx_empty_out <= rx_empty_out_comp(11);
|
416 |
|
|
end generate ag11;
|
417 |
|
|
|
418 |
|
|
ag12 : if n_ag_g > 12 generate
|
419 |
|
|
tx_av_in_comp(12) <= port12_tx_av_in;
|
420 |
|
|
tx_data_in_comp(13*data_width_g-1 downto 12*data_width_g) <= port12_tx_data_in;
|
421 |
|
|
tx_we_in_comp(12) <= port12_tx_we_in;
|
422 |
|
|
tx_txlen_in_comp(13*tx_len_width_g-1 downto 12*tx_len_width_g) <= port12_tx_txlen_in;
|
423 |
|
|
rx_re_in_comp(12) <= port12_rx_re_in;
|
424 |
|
|
|
425 |
|
|
port12_tx_full_out <= tx_full_out_comp(12);
|
426 |
|
|
port12_rx_av_out <= rx_av_out_comp(12);
|
427 |
|
|
port12_rx_data_out <= rx_data_out_comp(13*data_width_g-1 downto 12*data_width_g);
|
428 |
|
|
port12_rx_empty_out <= rx_empty_out_comp(12);
|
429 |
|
|
end generate ag12;
|
430 |
|
|
|
431 |
|
|
ag13 : if n_ag_g > 13 generate
|
432 |
|
|
tx_av_in_comp(13) <= port13_tx_av_in;
|
433 |
|
|
tx_data_in_comp(14*data_width_g-1 downto 13*data_width_g) <= port13_tx_data_in;
|
434 |
|
|
tx_we_in_comp(13) <= port13_tx_we_in;
|
435 |
|
|
tx_txlen_in_comp(14*tx_len_width_g-1 downto 13*tx_len_width_g) <= port13_tx_txlen_in;
|
436 |
|
|
rx_re_in_comp(13) <= port13_rx_re_in;
|
437 |
|
|
|
438 |
|
|
port13_tx_full_out <= tx_full_out_comp(13);
|
439 |
|
|
port13_rx_av_out <= rx_av_out_comp(13);
|
440 |
|
|
port13_rx_data_out <= rx_data_out_comp(14*data_width_g-1 downto 13*data_width_g);
|
441 |
|
|
port13_rx_empty_out <= rx_empty_out_comp(13);
|
442 |
|
|
end generate ag13;
|
443 |
|
|
|
444 |
|
|
ag14 : if n_ag_g > 14 generate
|
445 |
|
|
tx_av_in_comp(14) <= port14_tx_av_in;
|
446 |
|
|
tx_data_in_comp(15*data_width_g-1 downto 14*data_width_g) <= port14_tx_data_in;
|
447 |
|
|
tx_we_in_comp(14) <= port14_tx_we_in;
|
448 |
|
|
tx_txlen_in_comp(15*tx_len_width_g-1 downto 14*tx_len_width_g) <= port14_tx_txlen_in;
|
449 |
|
|
rx_re_in_comp(14) <= port14_rx_re_in;
|
450 |
|
|
|
451 |
|
|
port14_tx_full_out <= tx_full_out_comp(14);
|
452 |
|
|
port14_rx_av_out <= rx_av_out_comp(14);
|
453 |
|
|
port14_rx_data_out <= rx_data_out_comp(15*data_width_g-1 downto 14*data_width_g);
|
454 |
|
|
port14_rx_empty_out <= rx_empty_out_comp(14);
|
455 |
|
|
end generate ag14;
|
456 |
|
|
|
457 |
|
|
ag15 : if n_ag_g > 15 generate
|
458 |
|
|
tx_av_in_comp(15) <= port15_tx_av_in;
|
459 |
|
|
tx_data_in_comp(16*data_width_g-1 downto 15*data_width_g) <= port15_tx_data_in;
|
460 |
|
|
tx_we_in_comp(15) <= port15_tx_we_in;
|
461 |
|
|
tx_txlen_in_comp(16*tx_len_width_g-1 downto 15*tx_len_width_g) <= port15_tx_txlen_in;
|
462 |
|
|
rx_re_in_comp(15) <= port15_rx_re_in;
|
463 |
|
|
|
464 |
|
|
port15_tx_full_out <= tx_full_out_comp(15);
|
465 |
|
|
port15_rx_av_out <= rx_av_out_comp(15);
|
466 |
|
|
port15_rx_data_out <= rx_data_out_comp(16*data_width_g-1 downto 15*data_width_g);
|
467 |
|
|
port15_rx_empty_out <= rx_empty_out_comp(15);
|
468 |
|
|
end generate ag15;
|
469 |
|
|
|
470 |
|
|
|
471 |
|
|
the_network: ring_with_pkt_codec_top
|
472 |
|
|
generic map (
|
473 |
|
|
n_ag_g => n_ag_g,
|
474 |
|
|
stfwd_en_g => stfwd_en_g,
|
475 |
|
|
diag_en_g => diag_en_g,
|
476 |
|
|
data_width_g => data_width_g,
|
477 |
|
|
addr_width_g => addr_width_g,
|
478 |
|
|
packet_length_g => packet_length_g,
|
479 |
|
|
tx_len_width_g => tx_len_width_g,
|
480 |
|
|
timeout_g => timeout_g,
|
481 |
|
|
fill_packet_g => fill_packet_g,
|
482 |
|
|
lut_en_g => lut_en_g,
|
483 |
|
|
len_flit_en_g => len_flit_en_g,
|
484 |
|
|
oaddr_flit_en_g => oaddr_flit_en_g,
|
485 |
|
|
status_en_g => status_en_g,
|
486 |
|
|
fifo_depth_g => fifo_depth_g,
|
487 |
|
|
ring_freq_g => ring_freq_g,
|
488 |
|
|
ip_freq_g => ip_freq_g)
|
489 |
|
|
port map (
|
490 |
|
|
clk_net => clk_net,
|
491 |
|
|
clk_ip => clk_ip,
|
492 |
|
|
rst_n => rst_n,
|
493 |
|
|
tx_av_in => tx_av_in_comp,
|
494 |
|
|
tx_data_in => tx_data_in_comp,
|
495 |
|
|
tx_we_in => tx_we_in_comp,
|
496 |
|
|
tx_txlen_in => tx_txlen_in_comp,
|
497 |
|
|
tx_full_out => tx_full_out_comp,
|
498 |
|
|
tx_empty_out => open,
|
499 |
|
|
rx_av_out => rx_av_out_comp,
|
500 |
|
|
rx_data_out => rx_data_out_comp,
|
501 |
|
|
rx_re_in => rx_re_in_comp,
|
502 |
|
|
rx_empty_out => rx_empty_out_comp);
|
503 |
|
|
|
504 |
|
|
end structural;
|