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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [2.0/] [vhd/] [addr_data_demuxes.vhd] - Blame information for rev 145

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1 145 lanttu
-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE.  See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File        : addr_data_demuxes.vhdl
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-- Design:
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-- Project:
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-- e-mail : 
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-- Description : Converts separated addr+data signalling into multiplexed addr/data.
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--               Two components : one for writing and one for reading fifo.
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--               Input : addr + data muxed into one port
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--               Out   : separate addr + data ports
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--               
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-- Author      : Erno Salminen
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-- Date        : 16.01.2003
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-- Modified    : 
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--               
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-- 
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-- 05.02.2003   Name changed from fifo_demux_X to addr_data_demux_X
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-- 15.12.2004   ES names changed
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-- IP:lta tulee osoite ja data perakkain, siirretaan ne fifoon rinnakkain
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entity addr_data_demux_write is
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  generic (
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    data_width_g         :     integer := 0;
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    addr_width_g         :     integer := 0
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    );
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  port (
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    clk                : in  std_logic;
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    rst_n              : in  std_logic;
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    av_in     : in  std_logic;
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    data_in   : in  std_logic_vector ( data_width_g-1 downto 0);
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    we_in     : in  std_logic;
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    full_out  : out std_logic;
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    one_p_out : out std_logic;
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    we_out   : out std_logic;
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    data_out : out std_logic_vector ( data_width_g-1 downto 0);
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    addr_out : out std_logic_vector ( addr_width_g-1 downto 0);
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    full_in  : in  std_logic;
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    one_p_in : in  std_logic
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    );
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end addr_data_demux_write;
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architecture rtl of addr_data_demux_write is
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  signal addr_r        : std_logic_vector ( addr_width_g-1 downto 0);
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begin  -- rtl
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  Store_addr : process (clk, rst_n)
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  begin  -- process Store_addr
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    if rst_n = '0' then                 -- asynchronous reset (active low)
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      data_out <= (others => '0');
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      addr_out <= (others => '0');
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      we_out   <= '0';
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      addr_r   <= (others => '0');
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    elsif clk'event and clk = '1' then  -- rising clock edge
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      if we_in = '1' then
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        if av_in = '1' then
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          -- New addr
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          if full_in = '0' then
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            addr_r <= data_in;
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          else
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            addr_r <= addr_r;
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          end if;
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        else
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          -- New data
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          if full_in = '0' then
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            -- Prev write ready, write new data
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            data_out <= data_in;
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            addr_out <= addr_r;
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            we_out   <= '1';
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          else
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            -- Prev write is not ready yet
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            -- Keep all values
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          end if;                       --write_ready          
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        end if;                         --av
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      else
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        -- No new write
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      end if;                           --we
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    end if;                             --rst
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  end process Store_addr;
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end rtl;                                --addr_data_demux_write
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-------------------------------------------------------------------------------
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--entity addr_data_demux_read luetaan fifosta osoite ja perakkain ja siirretaan
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-- ne IP:lle rinnakkain
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-- File :
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-- Description: 
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-- Design:
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-- Project:
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-- e-mail :
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-- Author:     Erno Salminen
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-- Date :       2003
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-- Modified:
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-- 06.08.2004   ES, one_data_in/out removed
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity addr_data_demux_read is
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  generic (
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    data_width_g :    integer := 0;
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    addr_width_g :    integer := 0;
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    comm_width_g :    integer := 0
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    );
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  port (
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    clk          : in std_logic;
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    rst_n        : in std_logic;
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    av_in    : in  std_logic;
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    data_in  : in  std_logic_vector ( data_width_g-1 downto 0);
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    comm_in  : in  std_logic_vector ( comm_width_g-1 downto 0);
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    empty_in : in  std_logic;
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    re_out   : out std_logic;
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    re_in     : in  std_logic;
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    addr_out  : out std_logic_vector ( addr_width_g-1 downto 0);
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    data_out  : out std_logic_vector ( data_width_g-1 downto 0);
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    comm_out  : out std_logic_vector ( comm_width_g-1 downto 0);
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    empty_out : out std_logic
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    );
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end addr_data_demux_read;
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architecture rtl of addr_data_demux_read is
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  signal addr_r   : std_logic_vector (addr_width_g-1 downto 0);
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  signal re_r     : std_logic;
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  signal rd_rdy_r : std_logic;
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begin  -- rtl
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  -- 1) COMB PROC
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  Read_fifo : process (re_in, re_r, empty_in, av_in)
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  begin  -- process Read_fifo
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    -- 21.01.2003 kokeilukorjaus, saa nähdä toimiiko jos IP pitää koko ajan re=1
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    if empty_in = '1' then
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      -- Fifossa ei ole mitaan
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      re_out <= '0';
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    else
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      if av_in = '1' then
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        -- Demux reads addr
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        re_out <= re_r;
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      else
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        -- IP reads data
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        re_out <= re_in;
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      end if;
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    end if;
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  end process Read_fifo;
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  -- 2) COMB PROC
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  Assign_empty_out : process (empty_in, av_in)
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  begin  -- process Assign_empty_out
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    -- addr must read to register before it is tramsferred to reader.
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    -- Therefore, empty_out is asserted until addr is read from fifo. 
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    if empty_in = '1' then
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      -- Fifossa ei ole mitaan
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      empty_out <= '1';
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    else
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      if av_in = '1' then
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        empty_out <=  '1';
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      else
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        empty_out <= '0';
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      end if;
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    end if;
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  end process Assign_empty_out;
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  -- 3) COMB PROC
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  Demux_addr_data : process (data_in, av_in, comm_in,
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                             addr_r, empty_in)
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  begin  -- process Demux_addr_data
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    -- Fifo outputs are directed outputs when addr has been read to register
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    -- and there is data coming from fifo
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    if empty_in = '0' and av_in = '0' then
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      -- data coming from fifo
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      data_out <= data_in;
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      addr_out <= addr_r;
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      comm_out <= comm_in;
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    else
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      -- addr coming fifo or fifo empty 
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      data_out <= (others => '0');
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      addr_out <= (others => '0');
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      comm_out <= (others => '0');
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    end if;
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  end process Demux_addr_data;
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  -- 4) SEQ PROC
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  Store_addr : process (clk, rst_n)
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  begin  -- process Store_addr
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    -- Reads addr from fifo to register
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    -- read_ready goes 1 after each fifo read operation, either initiated
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    --  + by demux (=addr read). 
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    --  + by reader ip (=data read).
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    -- read_ready remains 1, if fifo became empty
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    --  
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    --  Read goes 0 if fifo is not empty and no read operation is performed,
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    --  see above.
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    if rst_n = '0' then                 -- asynchronous reset (active low)
283
      addr_r   <= (others => '0');
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      re_r     <= '0';
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      rd_rdy_r <= '1';
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    elsif clk'event and clk = '1' then  -- rising clock edge
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289
      if empty_in = '1' then
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        -- Fifo is empty, keep state
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        addr_r   <= addr_r;
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        re_r     <= '0';
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        rd_rdy_r <= rd_rdy_r;
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295
      else
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        -- Fifo not empty
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298
        if av_in = '1' then
299
          -- Fifo has addr, read it
300
          addr_r <= data_in;
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          -- Keep RE=1 for one cycle
303
          if re_r = '0' then
304
            re_r     <= '1';
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            rd_rdy_r <= '0';
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          else
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            re_r     <= '0';
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            rd_rdy_r <= '1';
309
          end if;  --re_r
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311
          --assert false report "New addr in fifo" severity note;
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313
        else
314
          -- Fifossa on lukematon data
315
          addr_r        <= addr_r;
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          re_r <= '0';
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          if re_in = '1' then
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            -- Reader ip perfroms read operation
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            rd_rdy_r <= '1';
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            --assert false report "IP reads addr+data" severity note;
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          else
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            -- Wait, until read ip performs read operation
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            rd_rdy_r <= '0';
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            --assert false report "Wait for IP to read addr+data" severity note;            
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          end if;  --re_in
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        end if;                         --av        
329
      end if;                           --empty_in
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    end if;                             --rst_n    
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  end process Store_addr;
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end rtl;                                --addr_data_demux_read

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