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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : cfg_mem.vhdl
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-- Description : Stores the configuration values. There can be more than one
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-- configuration pages.
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-- Author : Erno Salminen
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-- e-mail : erno.salminen@tut.fi
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-- Project : huuhaa
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-- Design : Do not use term design when you mean system
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-- Date : 29.04.2002
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-- Modified : Vesa Lahtinen 10.05.2002 Functionality added
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--
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-- 24.07.02 ES: removed outputs Curr_cycle and Time_Frame_Length
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-- 14.11.02 ES: changed the type of memory register
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-- 18.11.02 ES: time slot signal decoding separated
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-- 03.02.03 ES: comparison_type added
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-- 15.04.03 ES: base addr made constant to speed up the addr decoder
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-- 19.05.03 ES: counter_width changed to generic value
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-- 31.07.03 ES: added checks for illegal page and param nums
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-- In illegal cases, internal write and read enable
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-- signals are reset to zero
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--
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--
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-- 09.12.04 TK: bit width of ID and Num_Of_Agents signals/port changed
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-- from Counter_Width to ID_Width
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-- 15.12.04 ES: names changed
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-- 20.01.05 ES: constant for enabling/disabling read operation
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-- 21.01.05 ES: constant for enabling/disabling write operation
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-- -> enable=0 cfg_mem is rom, same code can be used for
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-- both ram and rom
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-- 03.02.05 ES addr_width_g is now in BITS! New generic cfg_rom_en_g
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-- added
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-- 28.02.05 ES generic cfg_we and cfg_re added, cfg_rom_en_g removed
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-- 16.12.05 ES Extra parameters are removed
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-- Use package for intializing time_slots
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-- TO DO: Time_slot_r should be implemented with records to benefit
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-- from the modified signal widths made by TK in 9.12.04
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.cfg_init_pkg.all; -- init values for tiem slots
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entity cfg_mem is
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generic (
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id_width_g : integer := 4;
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id_g : integer := 5;
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base_id_g : integer := 5;
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data_width_g : integer := 16; -- in bits. 14.12.05: TURHA??
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-- addr_width_g : integer := 16; -- in bits
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counter_width_g : integer := 8;
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cfg_addr_width_g : integer := 7; -- 16.12.05
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inv_addr_en_g : integer := 0;
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addr_g : integer := 46;
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prior_g : integer := 2;
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max_send_g : integer := 50;
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arb_type_g : integer := 0;
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n_agents_g : integer := 4;
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n_cfg_pages_g : integer := 1;
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n_time_slots_g : integer := 0;
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-- n_extra_params_g : integer := 0;
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cfg_re_g : integer := 0;
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cfg_we_g : integer := 0
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- addr_in could be narrower, since id is only in addr decoder
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addr_in : in std_logic_vector ( cfg_addr_width_g -1 downto 0); --04.03.05
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data_in : in std_logic_vector ( data_width_g -1 downto 0);
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re_in : in std_logic;
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we_in : in std_logic;
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curr_slot_ends_out : out std_logic;
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curr_slot_own_out : out std_logic;
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next_slot_starts_out : out std_logic;
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next_slot_own_out : out std_logic;
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dbg_out : out integer range 0 to 100; -- For debug
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data_out : out std_logic_vector ( data_width_g-1 downto 0);
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arb_type_out : out std_logic_vector ( 1 downto 0);
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n_agents_out : out std_logic_vector ( id_width_g-1 downto 0);
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max_send_out : out std_logic_vector ( counter_width_g-1 downto 0);
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prior_out : out std_logic_vector ( id_width_g-1 downto 0);
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pwr_mode_out : out std_logic_vector ( 1 downto 0)
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);
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end cfg_mem;
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architecture rtl of cfg_mem is
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-- Calculate minimum of 1 and "value"
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-- Required for reserving signals for tslots ans extra_params
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-- (Design compiler does not handle empty arrays (e.g. 0 downto -1),
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-- Precision handles them well)
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function max_with_1 (
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constant value : integer)
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return integer is
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begin -- max_with_1
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if value = 0 then
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return 1;
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else
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return value;
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end if;
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end max_with_1;
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constant n_time_slots_tmp_c : integer := max_with_1 ( n_time_slots_g);
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-- constant n_extra_params_tmp_c : integer := max_with_1 ( n_extra_params_g);
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function log2 (
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constant value : integer)
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return integer is
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variable temp : integer := 1;
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variable counter : integer := 0;
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begin -- log2
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-- Unbounded loops are NOT synthesizable
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-- while temp < value loop
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-- temp := temp*2;
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-- counter := counter+1;
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-- end loop;
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temp := 1;
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counter := 0;
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for i in 0 to 30 loop
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if temp < value then
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temp := temp*2;
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counter := counter+1;
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end if;
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end loop;
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return counter;
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end log2;
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constant page_addr_width_c : integer := log2 (n_cfg_pages_g) + 1;
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-- Calculate the maximum size of configuration
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-- memory page. There are 8 parameters and address (which nowadays requires exactly one
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-- place in mem), each time slots requires 3 parameters (start, stop, owner),
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-- and there may be some application specific parameters as well.
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-- E.g. if n_time_slots_g=n_extra_params_g=0 then page_size_c= 8+1+3+1= 13 parameters
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constant page_size_c : integer := 8 + 1 + ( n_time_slots_tmp_c * 3); -- + n_extra_params_tmp_c;
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-- 16.12.05
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constant param_addr_width_c : integer := log2 (page_size_c);
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constant cfg_addr_width_c : integer := param_addr_width_c + page_addr_width_c;
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-- Signals can be viewed from Modelsim. These are not used for any other purpose.
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signal pag : integer := page_addr_width_c;
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signal par : integer := param_addr_width_c;
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signal cfg_a : integer := cfg_addr_width_c;
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-- Logic for dbg_out adds roughly 16% to area (at least when 16b data is used)
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constant dbg_level : integer range 0 to 3 := 0; -- 0= no debug, use 0 for synthesis
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-- constant enable_cfg_read_c : integer range 0 to 1 := 1;
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-- constant enable_cfg_write_c : integer range 0 to 1 := 1-cfg_rom_en_g;
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-- Define indexes for parameters
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constant ind_cycle_c : integer := 0;
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constant ind_prior_c : integer := 1;
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constant ind_n_ag_c : integer := 2; -- Num of AGents
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constant ind_arb_c : integer := 3;
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constant ind_pwr_c : integer := 4;
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constant ind_msend_c : integer := 5;
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constant ind_frame_c : integer := 6; -- ei tarvita ellei ole slotteja!
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constant ind_inva_c : integer := 7; -- INVert Addr
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constant ind_baddr_c : integer := 8; -- address requires nowadays exactly one memory slot
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constant ind_tslot_c : integer := 9;
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constant ind_extra_c : integer := ind_tslot_c + (n_time_slots_tmp_c *3);
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-- Output registers for time slots
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signal curr_slot_ends_r : std_logic;
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signal curr_slot_own_r : std_logic;
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signal next_slot_starts_r : std_logic;
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signal next_slot_own_r : std_logic;
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-- Register for storing current page number,
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-- page number zero reserved for special purposes!
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signal curr_page_r : integer range 1 to n_cfg_pages_g;
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-- Own register type for clock cycle counters
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type curr_cycle_array_type is array ( 1 to n_cfg_pages_g) of std_logic_vector (counter_width_g-1 downto 0);
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signal curr_cycle_r : curr_cycle_array_type;
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-- Internal signals for address slices
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signal page_num : integer range 0 to n_cfg_pages_g;
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signal param_num : integer range 0 to page_size_c;
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-- Internal write and read enable
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-- If page and param numbers are valid, these are identical to inputs
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-- Otherwise, they are reset to zero
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signal we_int : std_logic;
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signal re_int : std_logic;
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-- Define type and register for configuration memory
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-- Use record instead of array => fields can have different widths
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type cfg_page_type is record
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Prior : std_logic_vector ( id_width_g-1 downto 0);
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N_ag : std_logic_vector ( id_width_g-1 downto 0);
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Arb : std_logic_vector ( 1 downto 0);
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Power : std_logic_vector ( 1 downto 0);
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MSend : std_logic_vector ( counter_width_g-1 downto 0);
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Frame : std_logic_vector ( counter_width_g-1 downto 0);
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--Inva : std_logic;
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end record;
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type cfg_array is array ( 1 to n_cfg_pages_g) of cfg_page_type;
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signal memory_r : cfg_array;
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-- Own register type for time slots (conf_page, time_slot_param)
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-- Note the indexing! This way the incoming addr can be used for indexing without modification..
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type tslot_page_type is array ( (ind_tslot_c) to (ind_tslot_c + 3*n_time_slots_tmp_c-1))
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of std_logic_vector ( counter_width_g-1 downto 0);
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type tslot_page_array_type is array (1 to n_cfg_pages_g) of tslot_page_type;
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signal tslot_r : tslot_page_array_type;
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-- 19.12.2005
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-- Slot owner needs (usually) less bits than start and stop times
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type tslot_start_type is array ( (ind_tslot_c) to (ind_tslot_c + 1*n_time_slots_tmp_c-1)) of std_logic_vector ( counter_width_g-1 downto 0);
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type tslot_stop_type is array ( (ind_tslot_c + 1*n_time_slots_tmp_c) to (ind_tslot_c + 2*n_time_slots_tmp_c-1)) of std_logic_vector ( counter_width_g-1 downto 0);
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type tslot_id_type is array ( (ind_tslot_c + 2*n_time_slots_tmp_c) to (ind_tslot_c + 3*n_time_slots_tmp_c-1)) of std_logic_vector ( id_width_g-1 downto 0);
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type tslot_start_array_type is array (1 to n_cfg_pages_g) of tslot_start_type;
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type tslot_stop_array_type is array (1 to n_cfg_pages_g) of tslot_stop_type;
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type tslot_id_array_type is array (1 to n_cfg_pages_g) of tslot_id_type;
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signal tslot_start_r : tslot_start_array_type;
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signal tslot_stop_r : tslot_stop_array_type;
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signal tslot_id_r : tslot_id_array_type;
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-- -- Own register type for extra parameters (conf_page, extra_param_num)
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-- -- Note the indexing! This way the incoming addr can be used for indexing without modification..
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-- -- type extra_param_page_type is array (ind_extra_c to ind_extra_c + n_extra_params_g-1)
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-- -- of std_logic_vector ( data_width_g-1 downto 0);
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-- type extra_param_page_type is array (ind_extra_c to ind_extra_c + n_extra_params_tmp_c-1)
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-- of std_logic_vector ( data_width_g-1 downto 0);
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-- type extra_param_array_type is array (1 to n_cfg_pages_g) of extra_param_page_type;
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-- signal extra_param_r : extra_param_array_type;
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begin -- rtl
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-- Continuous assignments
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curr_slot_ends_out <= curr_slot_ends_r;
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curr_slot_own_out <= curr_slot_own_r;
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next_slot_starts_out <= next_slot_starts_r;
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next_slot_own_out <= next_slot_own_r;
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prior_out <= memory_r (curr_page_r).Prior; --1
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n_agents_out <= memory_r (curr_page_r).N_ag; --2
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arb_type_out <= memory_r (curr_page_r).Arb; --3
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pwr_mode_out <= memory_r (curr_page_r).Power; --4
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max_send_out <= memory_r (curr_page_r).MSend; --5
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-- Check generic values
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-- assert (id_width_g + cfg_addr_width_g < addr_width_g+1) report
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-- "Illegal generic values (Id-, page- or param_addr_width_c" severity error;
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-- assert (param_addr_width_c + page_addr_width_c < cfg_addr_width_g+1) report
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-- "Illegal generic values (Id-, page- or param_addr_width_c" severity error;
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-- PROCESSES -----------------------------------------------------------------
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--
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-- 1) PROC
|
325 |
|
|
-- Split the incoming config address to separate page and parameter number.
|
326 |
|
|
-- Check incoming page and param numbers
|
327 |
|
|
-- If they are illegal, internal write and read enbale signals are reset to
|
328 |
|
|
-- zero => Nothing happens inside config mem, no checks needed elsewhere than here
|
329 |
|
|
--
|
330 |
|
|
Split_addr_in : process (addr_in,
|
331 |
|
|
we_in,
|
332 |
|
|
re_in
|
333 |
|
|
)
|
334 |
|
|
begin -- process Split_addr_in
|
335 |
|
|
if conv_integer ( addr_in ( page_addr_width_c + param_addr_width_c-1 downto param_addr_width_c)) > n_cfg_pages_g
|
336 |
|
|
or conv_integer ( addr_in ( param_addr_width_c-1 downto 0)) > page_size_c then
|
337 |
|
|
-- Illegal page or parameter number
|
338 |
|
|
page_num <= 0;
|
339 |
|
|
param_num <= 0;
|
340 |
|
|
we_int <= '0';
|
341 |
|
|
re_int <= '0';
|
342 |
|
|
assert false report "Illegal addr to cfg mem" severity note;
|
343 |
|
|
else
|
344 |
|
|
-- Valid page and parameter numbers
|
345 |
|
|
page_num <= conv_integer ( addr_in ( page_addr_width_c+param_addr_width_c-1 downto param_addr_width_c));
|
346 |
|
|
param_num <= conv_integer ( addr_in ( param_addr_width_c-1 downto 0));
|
347 |
|
|
we_int <= we_in;
|
348 |
|
|
re_int <= re_in;
|
349 |
|
|
end if;
|
350 |
|
|
|
351 |
|
|
end process Split_addr_in;
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
-- 2) PROC
|
356 |
|
|
-- Write new values to memory if needed, count clock cycles and time slots
|
357 |
|
|
Main : process (clk, rst_n)
|
358 |
|
|
|
359 |
|
|
variable Start_v : std_logic_vector( counter_width_g-1 downto 0);
|
360 |
|
|
variable Stop_v : std_logic_vector( counter_width_g-1 downto 0);
|
361 |
|
|
variable Owner_v : std_logic_vector( id_width_g-1 downto 0);
|
362 |
|
|
variable curr_slot_own_v : std_logic;
|
363 |
|
|
variable curr_slot_ends_v : std_logic;
|
364 |
|
|
variable next_slot_own_v : std_logic;
|
365 |
|
|
variable next_slot_starts_v : std_logic;
|
366 |
|
|
|
367 |
|
|
begin -- process Main
|
368 |
|
|
|
369 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
370 |
|
|
|
371 |
|
|
-- Reset cycle counter
|
372 |
|
|
for i in 1 to n_cfg_pages_g loop
|
373 |
|
|
curr_cycle_r (i) <= (others => '0'); -- vai 1?
|
374 |
|
|
end loop; -- i
|
375 |
|
|
|
376 |
|
|
-- Reset all values in memory
|
377 |
|
|
for i in 1 to n_cfg_pages_g loop
|
378 |
|
|
memory_r (i).Arb <= conv_std_logic_vector(arb_type_g, 2); -- 3
|
379 |
|
|
memory_r (i).Power <= (others => '0'); -- 4
|
380 |
|
|
memory_r (i).Frame <= conv_std_logic_vector (tframe_c (i), counter_width_g); -- 6
|
381 |
|
|
--memory_r (i).Frame <= conv_std_logic_vector (60, counter_width_g); -- (others => '0'); -- 6
|
382 |
|
|
--memory_r (i).Inva <= '0'; -- 7
|
383 |
|
|
end loop; -- i
|
384 |
|
|
|
385 |
|
|
-- Assign generic values to memory
|
386 |
|
|
for i in 1 to n_cfg_pages_g loop
|
387 |
|
|
memory_r (i).Prior <= conv_std_logic_vector ( prior_g, id_width_g);
|
388 |
|
|
memory_r (i).N_ag <= conv_std_logic_vector ( n_agents_g, id_width_g);
|
389 |
|
|
memory_r (i).MSend <= conv_std_logic_vector ( max_send_g, counter_width_g);
|
390 |
|
|
--if inv_addr_en_g = 0 then
|
391 |
|
|
-- memory_r (i).Inva <= '0';
|
392 |
|
|
--else
|
393 |
|
|
-- memory_r (i).Inva <= '1';
|
394 |
|
|
--end if;
|
395 |
|
|
|
396 |
|
|
end loop; -- i
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
if n_time_slots_g > 0 then --16.02.05
|
400 |
|
|
for p in 1 to n_cfg_pages_g loop
|
401 |
|
|
for s in 0 to n_time_slots_g-1 loop
|
402 |
|
|
tslot_r (p) (ind_tslot_c + s*3+0) <= conv_std_logic_vector (9,counter_width_g);
|
403 |
|
|
tslot_r (p) (ind_tslot_c + s*3+1) <= conv_std_logic_vector (13,counter_width_g);
|
404 |
|
|
tslot_r (p) (ind_tslot_c + s*3+2) <= conv_std_logic_vector (3,counter_width_g);
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
if p < (max_n_cfg_pages_c+1) and s < max_n_tslots_c then
|
408 |
|
|
|
409 |
|
|
tslot_start_r (p) (ind_tslot_c + s) <= conv_std_logic_vector (tslot_start_c (p) (s), counter_width_g);
|
410 |
|
|
tslot_stop_r (p) (ind_tslot_c + n_time_slots_tmp_c + s) <= conv_std_logic_vector (tslot_stop_c (p) (s), counter_width_g);
|
411 |
|
|
tslot_id_r (p) (ind_tslot_c + 2* n_time_slots_tmp_c + s) <= conv_std_logic_vector (tslot_id_c (p) (s), id_width_g);
|
412 |
|
|
|
413 |
|
|
else
|
414 |
|
|
tslot_start_r (p) (ind_tslot_c + s) <= (others => '0');
|
415 |
|
|
tslot_stop_r (p) (ind_tslot_c + n_time_slots_tmp_c + s) <= (others => '0');
|
416 |
|
|
tslot_id_r (p) (ind_tslot_c + 2* n_time_slots_tmp_c + s) <= (others => '0');
|
417 |
|
|
|
418 |
|
|
end if;
|
419 |
|
|
|
420 |
|
|
|
421 |
|
|
end loop; -- s
|
422 |
|
|
end loop; -- p
|
423 |
|
|
end if;
|
424 |
|
|
|
425 |
|
|
-- Reset extra parameters
|
426 |
|
|
-- for p in 1 to n_cfg_pages_g loop
|
427 |
|
|
-- for e in ind_extra_c to ind_extra_c+ n_extra_params_g-1 loop
|
428 |
|
|
-- extra_param_r (p) (e) <= (others => '0');
|
429 |
|
|
-- end loop; -- e
|
430 |
|
|
-- end loop; -- p
|
431 |
|
|
|
432 |
|
|
curr_page_r <= 1;
|
433 |
|
|
curr_slot_own_r <= '0';
|
434 |
|
|
curr_slot_ends_r <= '0';
|
435 |
|
|
next_slot_own_r <= '0';
|
436 |
|
|
next_slot_starts_r <= '0';
|
437 |
|
|
if dbg_level > 0 then dbg_out <= 55; end if;
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
442 |
|
|
|
443 |
|
|
-- default assignments
|
444 |
|
|
tslot_r <= tslot_r;
|
445 |
|
|
tslot_start_r <= tslot_start_r;
|
446 |
|
|
tslot_stop_r <= tslot_stop_r;
|
447 |
|
|
tslot_id_r <= tslot_id_r;
|
448 |
|
|
curr_cycle_r <= curr_cycle_r;
|
449 |
|
|
-- extra_param_r <= extra_param_r;
|
450 |
|
|
|
451 |
|
|
|
452 |
|
|
if cfg_we_g = 1
|
453 |
|
|
and we_int = '1'
|
454 |
|
|
then
|
455 |
|
|
|
456 |
|
|
if page_num = conv_std_logic_vector (0, page_addr_width_c) then
|
457 |
|
|
-- Special case when page num is zero
|
458 |
|
|
|
459 |
|
|
if param_num = conv_std_logic_vector ( 0, param_addr_width_c) then
|
460 |
|
|
-- Change page when both page and parameter number are zero
|
461 |
|
|
-- Check that the new page num is valid (i.e. not zero)
|
462 |
|
|
if data_in (page_addr_width_c-1 downto 0) <= n_cfg_pages_g
|
463 |
|
|
and data_in (page_addr_width_c-1 downto 0) /= conv_std_logic_vector (0, page_addr_width_c) -- 04.03.05
|
464 |
|
|
then
|
465 |
|
|
|
466 |
|
|
curr_page_r <= conv_integer (data_in ( page_addr_width_c-1 downto 0));
|
467 |
|
|
memory_r <= memory_r;
|
468 |
|
|
--assert false report "Change page number" severity note;
|
469 |
|
|
if dbg_level > 0 then dbg_out <= 100; end if;
|
470 |
|
|
else
|
471 |
|
|
-- Galaxies will explode, if illegal page number is written into
|
472 |
|
|
-- curr page register
|
473 |
|
|
curr_page_r <= curr_page_r;
|
474 |
|
|
memory_r <= memory_r;
|
475 |
|
|
assert false report "Switch to illegal page number cancelled!" severity note;
|
476 |
|
|
if dbg_level > 0 then dbg_out <= 80; end if;
|
477 |
|
|
end if; --data_in
|
478 |
|
|
else
|
479 |
|
|
-- page num zero, but param num is not => do nothing
|
480 |
|
|
curr_page_r <= curr_page_r;
|
481 |
|
|
memory_r <= memory_r;
|
482 |
|
|
if dbg_level > 0 then dbg_out <= 81; end if;
|
483 |
|
|
end if; -- param_num =0
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
else
|
487 |
|
|
-- 0 < page_num < n_cfg_pages_g
|
488 |
|
|
-- Write new parameter value
|
489 |
|
|
curr_page_r <= curr_page_r;
|
490 |
|
|
memory_r <= memory_r;
|
491 |
|
|
|
492 |
|
|
if param_num < ind_tslot_c then
|
493 |
|
|
-- if param_num < ind_baddr_c then
|
494 |
|
|
case param_num is
|
495 |
|
|
when ind_cycle_c =>
|
496 |
|
|
-- param=0, different reg for cycle count
|
497 |
|
|
-- Updated elsewhere
|
498 |
|
|
if dbg_level > 0 then dbg_out <= ind_cycle_c; end if;
|
499 |
|
|
when ind_prior_c =>
|
500 |
|
|
memory_r (page_num).Prior <= data_in ( id_width_g-1 downto 0); -- param = 1
|
501 |
|
|
if dbg_level > 0 then dbg_out <= ind_prior_c; end if;
|
502 |
|
|
when ind_n_ag_c =>
|
503 |
|
|
memory_r (page_num).N_ag <= data_in ( id_width_g-1 downto 0); -- param = 2
|
504 |
|
|
if dbg_level > 0 then dbg_out <= ind_n_ag_c; end if;
|
505 |
|
|
when ind_arb_c =>
|
506 |
|
|
memory_r (page_num).Arb <= data_in (1 downto 0); -- param = 3
|
507 |
|
|
if dbg_level > 0 then dbg_out <= ind_arb_c; end if;
|
508 |
|
|
when ind_pwr_c =>
|
509 |
|
|
memory_r (page_num).Power <= data_in (1 downto 0); -- param = 4
|
510 |
|
|
if dbg_level > 0 then dbg_out <= ind_pwr_c; end if;
|
511 |
|
|
when ind_msend_c =>
|
512 |
|
|
memory_r (page_num).MSend <= data_in ( counter_width_g-1 downto 0); -- param = 5
|
513 |
|
|
if dbg_level > 0 then dbg_out <= ind_msend_c; end if;
|
514 |
|
|
when ind_frame_c =>
|
515 |
|
|
if n_time_slots_g > 0 then -- 24.01.05
|
516 |
|
|
memory_r (page_num).Frame <= data_in ( counter_width_g-1 downto 0); -- param = 6
|
517 |
|
|
end if;
|
518 |
|
|
if dbg_level > 0 then dbg_out <= ind_frame_c; end if;
|
519 |
|
|
when ind_inva_c =>
|
520 |
|
|
--memory_r (page_num).Inva <= data_in ( 0); -- param = 7
|
521 |
|
|
if dbg_level > 0 then dbg_out <= ind_inva_c; end if;
|
522 |
|
|
assert false report "Trying to write address invert enable" severity warning;
|
523 |
|
|
|
524 |
|
|
when ind_baddr_c => -- param = 8
|
525 |
|
|
-- moved here 16.12.2005
|
526 |
|
|
-- Address is now constant, do not updata
|
527 |
|
|
if dbg_level > 0 then dbg_out <= ind_baddr_c; end if;
|
528 |
|
|
assert false report "Trying to write address" severity warning;
|
529 |
|
|
|
530 |
|
|
when others =>
|
531 |
|
|
assert false report "Incorrect parameter number" severity warning;
|
532 |
|
|
if dbg_level > 0 then dbg_out <= 99; end if;
|
533 |
|
|
end case;
|
534 |
|
|
|
535 |
|
|
else
|
536 |
|
|
-- 16.12.2005 elsif param_num < ind_extra_c then
|
537 |
|
|
-- Assign time slot parameters
|
538 |
|
|
if n_time_slots_g > 0 then
|
539 |
|
|
tslot_r (page_num) ( param_num) <= data_in (counter_width_g-1 downto 0);
|
540 |
|
|
|
541 |
|
|
if param_num < (ind_tslot_c + n_time_slots_tmp_c) then
|
542 |
|
|
tslot_start_r (page_num) ( param_num) <= data_in (counter_width_g-1 downto 0);
|
543 |
|
|
|
544 |
|
|
elsif param_num < (ind_tslot_c + 2*n_time_slots_tmp_c) then
|
545 |
|
|
tslot_stop_r (page_num) ( param_num) <= data_in (counter_width_g-1 downto 0);
|
546 |
|
|
|
547 |
|
|
else
|
548 |
|
|
tslot_id_r (page_num) ( param_num) <= data_in (id_width_g-1 downto 0);
|
549 |
|
|
end if;
|
550 |
|
|
|
551 |
|
|
|
552 |
|
|
|
553 |
|
|
end if;
|
554 |
|
|
assert dbg_level < 1 report "Set time slots" severity note;
|
555 |
|
|
if dbg_level > 0 then dbg_out <= ind_tslot_c; end if;
|
556 |
|
|
|
557 |
|
|
-- else
|
558 |
|
|
-- -- Assign extra parameters
|
559 |
|
|
-- if n_extra_params_g > 0 then
|
560 |
|
|
-- extra_param_r (page_num) (param_num) <= data_in;
|
561 |
|
|
-- end if;
|
562 |
|
|
-- assert dbg_level < 1 report "Set extra params" severity note;
|
563 |
|
|
-- if dbg_level > 0 then dbg_out <= ind_extra_c; end if;
|
564 |
|
|
end if; -- param_num >= ind_baddr_c
|
565 |
|
|
end if; -- page_num =0
|
566 |
|
|
|
567 |
|
|
else
|
568 |
|
|
-- WE =0 or illegal addr => memory_r remains static
|
569 |
|
|
curr_page_r <= curr_page_r;
|
570 |
|
|
--memory_r <= memory_r;
|
571 |
|
|
if dbg_level > 0 then dbg_out <= 64; end if;
|
572 |
|
|
end if; -- WE =1
|
573 |
|
|
|
574 |
|
|
|
575 |
|
|
-- Counters are only needed for time slots
|
576 |
|
|
if n_time_slots_g > 0 then
|
577 |
|
|
|
578 |
|
|
-- Clock cycle counter (parameter number is 0)
|
579 |
|
|
if param_num = conv_std_logic_vector (0, param_addr_width_c)
|
580 |
|
|
and page_num /= conv_std_logic_vector (0, page_addr_width_c)
|
581 |
|
|
and we_int = '1' then
|
582 |
|
|
|
583 |
|
|
-- Write new value to curr cycle register
|
584 |
|
|
|
585 |
|
|
if page_num = curr_page_r then
|
586 |
|
|
-- Write on current page
|
587 |
|
|
curr_cycle_r <= curr_cycle_r; --just in case
|
588 |
|
|
curr_cycle_r (curr_page_r) <= data_in (counter_width_g-1 downto 0);
|
589 |
|
|
else
|
590 |
|
|
-- Write to inactive page, clock cycle on current page is incremented
|
591 |
|
|
curr_cycle_r <= curr_cycle_r; --just in case
|
592 |
|
|
curr_cycle_r (page_num) <= data_in (counter_width_g-1 downto 0);
|
593 |
|
|
|
594 |
|
|
-- Clock cycle counter goes from 1 to FrameLength
|
595 |
|
|
-- counter is reseted to 1
|
596 |
|
|
if (curr_cycle_r (curr_page_r) = memory_r (curr_page_r).Frame
|
597 |
|
|
and (memory_r (curr_page_r).Frame) /= conv_std_logic_vector (0, counter_width_g) ) then --04.03.05
|
598 |
|
|
-- and (memory_r (curr_page_r).Frame) /= conv_std_logic_vector (0, data_width_g) ) then
|
599 |
|
|
curr_cycle_r (curr_page_r) <= conv_std_logic_vector (1, counter_width_g);
|
600 |
|
|
else
|
601 |
|
|
curr_cycle_r (curr_page_r) <= curr_cycle_r (curr_page_r) + 1;
|
602 |
|
|
end if;
|
603 |
|
|
end if; --page_num = curr_page_r
|
604 |
|
|
|
605 |
|
|
else
|
606 |
|
|
-- current clock counter is incremented
|
607 |
|
|
|
608 |
|
|
curr_cycle_r <= curr_cycle_r;
|
609 |
|
|
-- Clock cycle counter goes from 1 to FrameLength
|
610 |
|
|
if (curr_cycle_r (curr_page_r) = memory_r (curr_page_r).Frame
|
611 |
|
|
and (memory_r (curr_page_r).Frame) /= conv_std_logic_vector (0, counter_width_g) ) then --04.03.05
|
612 |
|
|
--and (memory_r (curr_page_r).Frame) /= conv_std_logic_vector (0, data_width_g) )then
|
613 |
|
|
-- counter is reseted to 1
|
614 |
|
|
curr_cycle_r (curr_page_r) <= conv_std_logic_vector(1, counter_width_g);
|
615 |
|
|
else
|
616 |
|
|
curr_cycle_r (curr_page_r) <= curr_cycle_r (curr_page_r) + 1;
|
617 |
|
|
end if;
|
618 |
|
|
end if; --param_num =ind_cycle_c+1
|
619 |
|
|
|
620 |
|
|
end if; -- n_time_slots_g 24.01.05
|
621 |
|
|
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
|
625 |
|
|
-- Time slot signals are produced with a loop
|
626 |
|
|
|
627 |
|
|
-- Goal: Bus is reserved one cycle after start=1
|
628 |
|
|
-- and start writing on the cycle following reservation
|
629 |
|
|
-- However, bus is released (lock=0) on the cycle following end=1
|
630 |
|
|
-- The last data is written into bus at the time as lock=0
|
631 |
|
|
curr_slot_own_v := '0';
|
632 |
|
|
curr_slot_ends_v := '0';
|
633 |
|
|
next_slot_own_v := '0';
|
634 |
|
|
next_slot_starts_v := '0';
|
635 |
|
|
|
636 |
|
|
for i in 0 to n_time_slots_g - 1 loop
|
637 |
|
|
|
638 |
|
|
Start_v := tslot_start_r (curr_page_r)(ind_tslot_c + i);
|
639 |
|
|
Stop_v := tslot_stop_r (curr_page_r)(ind_tslot_c + n_time_slots_tmp_c + i);
|
640 |
|
|
Owner_v := tslot_id_r (curr_page_r)(ind_tslot_c + 2 * n_time_slots_tmp_c + i);
|
641 |
|
|
|
642 |
|
|
--Start_v := tslot_r (curr_page_r)(ind_tslot_c + 3 * i);
|
643 |
|
|
--Stop_v := tslot_r (curr_page_r)(ind_tslot_c + 3 * i + 1);
|
644 |
|
|
--Owner_v := tslot_r (curr_page_r)(ind_tslot_c + 3 * i + 2)(id_width_g-1 downto 0);
|
645 |
|
|
|
646 |
|
|
|
647 |
|
|
|
648 |
|
|
-- Will current time slot end
|
649 |
|
|
-- elsif makes sure that active bit one is not overwritten
|
650 |
|
|
-- (when rest of the time slots are compared)
|
651 |
|
|
if (curr_cycle_r (curr_page_r) = Stop_v) then
|
652 |
|
|
curr_slot_ends_v := '1';
|
653 |
|
|
elsif (curr_slot_ends_v = '1') then
|
654 |
|
|
curr_slot_ends_v := '1';
|
655 |
|
|
else
|
656 |
|
|
curr_slot_ends_v := '0';
|
657 |
|
|
end if;
|
658 |
|
|
|
659 |
|
|
-- Will own time slot start next
|
660 |
|
|
if ( (curr_cycle_r (curr_page_r) = Start_v)
|
661 |
|
|
and (Owner_v = conv_std_logic_vector (id_g, id_width_g))) then
|
662 |
|
|
next_slot_own_v := '1';
|
663 |
|
|
elsif (next_slot_own_v = '1') then
|
664 |
|
|
next_slot_own_v := '1';
|
665 |
|
|
else
|
666 |
|
|
next_slot_own_v := '0';
|
667 |
|
|
end if;
|
668 |
|
|
|
669 |
|
|
-- Will some other time slot (not own) start next
|
670 |
|
|
if (curr_cycle_r (curr_page_r) = Start_v) then
|
671 |
|
|
next_slot_starts_v := '1';
|
672 |
|
|
elsif (next_slot_starts_v = '1') then
|
673 |
|
|
next_slot_starts_v := '1';
|
674 |
|
|
else
|
675 |
|
|
next_slot_starts_v := '0';
|
676 |
|
|
end if;
|
677 |
|
|
|
678 |
|
|
-- current time slot is own, if
|
679 |
|
|
-- 1) own time slot starts now
|
680 |
|
|
-- 2) already found a matching slot
|
681 |
|
|
-- 3) own time slot on the run
|
682 |
|
|
-- 4) AND time slot does not stop now
|
683 |
|
|
-- 5) AND no other slot will start (see below)
|
684 |
|
|
-- During reconfiguration, clock cycle may jump to value
|
685 |
|
|
-- that does not belong into any slot. Consequently, the
|
686 |
|
|
-- agent initializing reconfiguration may think that it still
|
687 |
|
|
-- has the slot (curr_own=1). This 'extra' piece of time slot
|
688 |
|
|
-- ends at least when some other agent starts its own slot.
|
689 |
|
|
-- It should be noted that stop signal may be absent in such situation
|
690 |
|
|
-- (because actually there is no slot)
|
691 |
|
|
--
|
692 |
|
|
|
693 |
|
|
if ( (next_slot_starts_r = '1' and next_slot_own_r = '1' ) -- 1
|
694 |
|
|
or (curr_slot_own_v = '1' or curr_slot_own_r = '1') ) -- 2 & 3
|
695 |
|
|
and curr_slot_ends_r = '0' -- 4
|
696 |
|
|
and not (next_slot_starts_r = '1' and next_slot_own_r = '0' ) -- 5
|
697 |
|
|
then
|
698 |
|
|
|
699 |
|
|
curr_slot_own_v := '1';
|
700 |
|
|
|
701 |
|
|
else
|
702 |
|
|
curr_slot_own_v := '0';
|
703 |
|
|
end if;
|
704 |
|
|
|
705 |
|
|
end loop; -- i
|
706 |
|
|
|
707 |
|
|
-- Assign output register values
|
708 |
|
|
curr_slot_own_r <= curr_slot_own_v;
|
709 |
|
|
curr_slot_ends_r <= curr_slot_ends_v;
|
710 |
|
|
next_slot_own_r <= next_slot_own_v;
|
711 |
|
|
next_slot_starts_r <= next_slot_starts_v;
|
712 |
|
|
|
713 |
|
|
|
714 |
|
|
end if; -- rst_n elsif clk'event
|
715 |
|
|
end process Main;
|
716 |
|
|
|
717 |
|
|
|
718 |
|
|
|
719 |
|
|
-- 3) PROC
|
720 |
|
|
Reading_values : process (re_int, page_num, param_num, memory_r,
|
721 |
|
|
curr_page_r, curr_cycle_r,
|
722 |
|
|
tslot_r,
|
723 |
|
|
tslot_start_r, tslot_stop_r, tslot_id_r --, extra_param_r
|
724 |
|
|
)
|
725 |
|
|
begin -- process Reading_values
|
726 |
|
|
|
727 |
|
|
-- 28.02.2005, Design compiler uses latches without this
|
728 |
|
|
-- default assignment
|
729 |
|
|
data_out <= (others => '0');
|
730 |
|
|
|
731 |
|
|
if cfg_re_g = 1 then
|
732 |
|
|
if re_int = '1' then
|
733 |
|
|
|
734 |
|
|
if page_num = 0 then
|
735 |
|
|
if param_num = 0 then
|
736 |
|
|
-- Read curr page number
|
737 |
|
|
data_out <= conv_std_logic_vector (curr_page_r, data_width_g);
|
738 |
|
|
|
739 |
|
|
elsif param_num = 1 then
|
740 |
|
|
-- Read ID
|
741 |
|
|
data_out <= conv_std_logic_vector (id_g, data_width_g);
|
742 |
|
|
|
743 |
|
|
elsif param_num = 2 then
|
744 |
|
|
-- Read base ID
|
745 |
|
|
data_out <= conv_std_logic_vector (base_id_g, data_width_g);
|
746 |
|
|
end if;
|
747 |
|
|
|
748 |
|
|
elsif page_num > n_cfg_pages_g or param_num > page_size_c then
|
749 |
|
|
-- Read either a non-existent param or from non-existent page
|
750 |
|
|
data_out <= (others => '0'); -- 'Z'); NOTE:'Z' only for test purposes!
|
751 |
|
|
assert false report "Illegal addres : I though this is obsolete line in code" severity WARNING;
|
752 |
|
|
-- Obsolete since 31.07 ??
|
753 |
|
|
-- Read enable should be reseted to zero, and this branch cannot be reached
|
754 |
|
|
|
755 |
|
|
else
|
756 |
|
|
-- Read a regular parameter
|
757 |
|
|
-- that means 0 < page < n_cfg_pages_g
|
758 |
|
|
|
759 |
|
|
if param_num < ind_tslot_c then
|
760 |
|
|
-- if param_num < ind_baddr_c then
|
761 |
|
|
case param_num is
|
762 |
|
|
when ind_cycle_c =>
|
763 |
|
|
data_out <= (others => '0');
|
764 |
|
|
data_out (counter_width_g-1 downto 0) <= curr_cycle_r ( page_num); --param = 0
|
765 |
|
|
|
766 |
|
|
when ind_prior_c =>
|
767 |
|
|
data_out <= (others => '0');
|
768 |
|
|
data_out (id_width_g-1 downto 0) <= memory_r (page_num).Prior; -- param = 1
|
769 |
|
|
|
770 |
|
|
when ind_n_ag_c =>
|
771 |
|
|
data_out <= (others => '0');
|
772 |
|
|
data_out (id_width_g-1 downto 0) <= memory_r (page_num).N_ag; -- param = 2
|
773 |
|
|
|
774 |
|
|
when ind_arb_c =>
|
775 |
|
|
data_out <= (others => '0');
|
776 |
|
|
data_out ( 1 downto 0) <= memory_r (page_num).Arb; -- param = 3
|
777 |
|
|
|
778 |
|
|
when ind_pwr_c =>
|
779 |
|
|
data_out <= (others => '0');
|
780 |
|
|
data_out ( 1 downto 0) <= memory_r (page_num).Power; -- param = 4
|
781 |
|
|
|
782 |
|
|
when ind_msend_c =>
|
783 |
|
|
data_out <= (others => '0');
|
784 |
|
|
data_out (counter_width_g-1 downto 0) <= memory_r (page_num).MSend; -- param = 5
|
785 |
|
|
|
786 |
|
|
when ind_frame_c =>
|
787 |
|
|
data_out <= (others => '0');
|
788 |
|
|
data_out (counter_width_g-1 downto 0) <= memory_r (page_num).Frame; -- param = 6
|
789 |
|
|
|
790 |
|
|
when ind_inva_c =>
|
791 |
|
|
data_out <= (others => '0');
|
792 |
|
|
-- data_out ( 0) <= memory_r (page_num).Inva; -- param = 7
|
793 |
|
|
data_out <= conv_std_logic_vector (inv_addr_en_g, data_width_g);
|
794 |
|
|
|
795 |
|
|
when ind_baddr_c => --param = 8
|
796 |
|
|
-- Moved here 16.12.2005
|
797 |
|
|
-- Read address
|
798 |
|
|
assert false report "Read address" severity note;
|
799 |
|
|
data_out <= conv_std_logic_vector ( addr_g, data_width_g); --14.04
|
800 |
|
|
|
801 |
|
|
when others =>
|
802 |
|
|
data_out <= (others => '0');
|
803 |
|
|
assert false report "Incorrect parameter number" severity warning;
|
804 |
|
|
end case;
|
805 |
|
|
|
806 |
|
|
|
807 |
|
|
else -- 16.12.2005
|
808 |
|
|
-- elsif param_num >= ind_tslot_c and param_num < ind_extra_c then
|
809 |
|
|
-- Read time slot parameters
|
810 |
|
|
-- param = (ind_tslot_c, ind_tslot_c + n_tslots-1)
|
811 |
|
|
data_out <= (others => '0');
|
812 |
|
|
if n_time_slots_g > 0 then
|
813 |
|
|
data_out (counter_width_g-1 downto 0) <= tslot_r (page_num) ( param_num);
|
814 |
|
|
|
815 |
|
|
if param_num < (ind_tslot_c + n_time_slots_tmp_c) then
|
816 |
|
|
data_out (counter_width_g-1 downto 0) <= tslot_start_r (page_num) ( param_num);
|
817 |
|
|
|
818 |
|
|
elsif param_num < (ind_tslot_c + 2*n_time_slots_tmp_c) then
|
819 |
|
|
data_out (counter_width_g-1 downto 0) <= tslot_stop_r (page_num) ( param_num);
|
820 |
|
|
|
821 |
|
|
else
|
822 |
|
|
data_out (id_width_g-1 downto 0) <= tslot_id_r (page_num) ( param_num);
|
823 |
|
|
end if;
|
824 |
|
|
|
825 |
|
|
end if;
|
826 |
|
|
assert dbg_level < 1 report "Read time slots" severity note;
|
827 |
|
|
|
828 |
|
|
|
829 |
|
|
-- Removed 16.12.2005
|
830 |
|
|
-- else
|
831 |
|
|
-- -- Read extra parameters
|
832 |
|
|
-- -- param = (ind_extra_c, ind_extra_c + n_extra_params_g-1)
|
833 |
|
|
-- data_out <= (others => '0');
|
834 |
|
|
-- if n_extra_params_g > 0 then
|
835 |
|
|
-- data_out <= extra_param_r (page_num) (param_num);
|
836 |
|
|
-- end if;
|
837 |
|
|
-- assert dbg_level < 1 report "Read extra params" severity note;
|
838 |
|
|
|
839 |
|
|
end if; -- param_num < ind_baddr_c
|
840 |
|
|
end if; -- page_num = 0
|
841 |
|
|
else
|
842 |
|
|
data_out <= (others => '0');
|
843 |
|
|
end if; --re_int
|
844 |
|
|
else
|
845 |
|
|
data_out <= (others => '0');
|
846 |
|
|
end if; -- cfg_re_g
|
847 |
|
|
end process Reading_values;
|
848 |
|
|
|
849 |
|
|
|
850 |
|
|
|
851 |
|
|
end rtl;
|