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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : double_fifo_demux_wr.vhd
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-- Description : Double_Fifo_Demux_wr buffer for hibi v.2 interface
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-- Includes two fifos and a special demultiplexer,
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-- has 1 input and 2 output ports
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-- so that the writer sees only one fifo. Demultiplexer
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-- directs addr+data to correct fifo (0 = for messages)
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--
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-- This version includes an extra fifo at the input the to get
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-- One_Place_Left_Out and Full_Out signals correctly timed
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--
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-- Author : Erno salminen
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-- e-mail : erno.salminen@tut.fi
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-- Project : huuhaa
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-- Design : Do not use term design when you mean system
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-- Date : 08.04.2003
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-- Modified :
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-- 24.07.03 ES added extra fifo in input, changed file name. Extra fifo
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-- provides signals "full" and "one_p" correctly
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--18.12.2006 AK modified to support different kinds of IF fifos
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity double_fifo_demux_wr is
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generic (
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-- 0 synch multiclk, 1 basic GALS,
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-- 2 Gray FIFO (depth=2^n!), 3 mixed clock pausible
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fifo_sel_g : integer := 0;
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-- needed for fifos 0 (accurate) and 3 (which is faster)
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re_freq_g : integer := 1;
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we_freq_g : integer := 1;
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depth_0_g : integer := 5;
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depth_1_g : integer := 5;
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data_width_g : integer := 32;
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debug_width_g : integer := 0;
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comm_width_g : integer := 3
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);
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port (
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clk_re : in std_logic;
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clk_we : in std_logic;
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-- pulsed clocks. used in pausible clock scheme
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clk_re_pls : in std_logic;
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clk_we_pls : in std_logic;
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rst_n : in std_logic;
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av_in : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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comm_in : in std_logic_vector (comm_width_g-1 downto 0);
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we_in : in std_logic;
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one_p_out : out std_logic;
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full_out : out std_logic;
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re_0_in : in std_logic;
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av_0_out : out std_logic;
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data_0_out : out std_logic_vector (data_width_g-1 downto 0);
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comm_0_out : out std_logic_vector (comm_width_g-1 downto 0);
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empty_0_out : out std_logic;
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one_d_0_out : out std_logic;
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re_1_in : in std_logic;
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av_1_out : out std_logic;
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data_1_out : out std_logic_vector (data_width_g-1 downto 0);
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comm_1_out : out std_logic_vector (comm_width_g-1 downto 0);
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empty_1_out : out std_logic;
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debug_out : out std_logic_vector(debug_width_g downto 0);
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one_d_1_out : out std_logic
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);
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end double_fifo_demux_wr;
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architecture structural of double_fifo_demux_wr is
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constant re_faster_c : integer := re_freq_g/we_freq_g;
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component mixed_clk_fifo
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generic (
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-- re_freq_g : integer := 0; -- integer multiple of clk_we
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-- we_freq_g : integer := 0; -- or vice versa
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re_faster_g : integer := 0;
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data_width_g : integer := 0;
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depth_g : integer := 0
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);
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port (
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clk_re : in std_logic;
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clk_we : in std_logic;
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clk_ps_re : in std_logic; -- phase shifted pulse
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clk_ps_we : in std_logic; -- phase shifted pulse
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rst_n : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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we_in : in std_logic;
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full_out : out std_logic;
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one_p_out : out std_logic;
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re_in : in std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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empty_out : out std_logic;
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one_d_out : out std_logic
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);
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end component; --fifo;
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component multiclk_fifo
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generic (
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re_freq_g : integer;
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we_freq_g : integer;
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depth_g : integer;
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data_width_g : integer);
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port (
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clk_re : in std_logic;
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clk_we : in std_logic;
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rst_n : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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we_in : in std_logic;
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full_out : out std_logic;
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one_p_out : out std_logic;
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re_in : in std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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empty_out : out std_logic;
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one_d_out : out std_logic);
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end component;
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component cdc_fifo
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generic (
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READ_AHEAD_g : integer;
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SYNC_CLOCKS_g : integer;
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depth_log2_g : integer;
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dataw_g : integer);
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port (
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rst_n : in std_logic;
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rd_clk : in std_logic;
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rd_en_in : in std_logic;
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rd_one_d_out : out std_logic;
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rd_empty_out : out std_logic;
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rd_data_out : out std_logic_vector(dataw_g-1 downto 0);
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wr_clk : in std_logic;
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wr_en_in : in std_logic;
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wr_full_out : out std_logic;
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wr_one_p_out : out std_logic;
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wr_data_in : in std_logic_vector(dataw_g-1 downto 0));
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end component;
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component fifo
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generic (
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data_width_g : integer := 0;
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depth_g : integer := 0
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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we_in : in std_logic;
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full_out : out std_logic;
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one_p_out : out std_logic;
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re_in : in std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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empty_out : out std_logic;
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one_d_out : out std_logic
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);
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end component; --fifo;
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component fifo_demux_wr
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generic (
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data_width_g : integer := 0;
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comm_width_g : integer := 0
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);
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port (
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-- 13.04 clk : in std_logic;
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-- 13.04 rst_n : in std_logic;
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av_in : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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comm_in : in std_logic_vector (comm_width_g-1 downto 0);
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we_in : in std_logic;
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full_out : out std_logic;
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one_p_out : out std_logic;
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-- data/comm/AV conencted to both fifos
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-- Distinction made with WE!
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av_out : out std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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we_0_out : out std_logic;
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we_1_out : out std_logic;
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full_0_in : in std_logic;
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full_1_in : in std_logic;
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one_p_0_in : in std_logic;
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one_p_1_in : in std_logic
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);
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end component;
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-- inputs to extra fifo (xf)
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signal a_c_d_input_xf : std_logic_vector (1 + comm_width_g + data_width_g-1 downto 0);
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-- from extra fifo to demux, 24.07 es
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signal a_c_d_xf_demux : std_logic_vector (1 + comm_width_g + data_width_g-1 downto 0);
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signal data_xf_demux : std_logic_vector (data_width_g-1 downto 0);
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signal comm_xf_demux : std_logic_vector (comm_width_g-1 downto 0);
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signal av_xf_demux : std_logic;
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signal empty_xf_demux : std_logic;
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signal we_xf_demux : std_logic;
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signal re_demux_xf : std_logic;
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signal full_demux_xf : std_logic;
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-- signal one_p_demux_xf : std_logic; ei tarvi
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-- signals to fifos (either from inputs or from demux)
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signal a_c_d_to_f01 : std_logic_vector (1 + comm_width_g + data_width_g-1 downto 0);
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signal we_to_f0 : std_logic;
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signal full_from_f0 : std_logic;
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signal one_p_from_f0 : std_logic;
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signal we_to_f1 : std_logic;
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signal full_from_f1 : std_logic;
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signal one_p_from_f1 : std_logic;
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-- from fifos to output
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signal a_c_d_f0_output : std_logic_vector (1 + comm_width_g + data_width_g-1 downto 0);
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signal a_c_d_f1_output : std_logic_vector (1 + comm_width_g + data_width_g-1 downto 0);
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-- logical zero and one
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signal Tie_High : std_logic;
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signal Tie_Low : std_logic;
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component aif_read_top
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generic (
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data_width_g : integer);
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port (
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tx_clk : in std_logic;
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tx_rst_n : in std_logic;
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tx_data_in : in std_logic_vector(data_width_g-1 downto 0);
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tx_empty_in : in std_logic;
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tx_re_out : out std_logic;
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rx_clk : in std_logic;
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rx_rst_n : in std_logic;
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rx_empty_out : out std_logic;
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rx_re_in : in std_logic;
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rx_data_out : out std_logic_vector(data_width_g-1 downto 0));
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end component;
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signal tx_data_to_aif : std_logic_vector(1+comm_width_g+data_width_g-1 downto 0);
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signal tx_empty_to_aif : std_logic;
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signal tx_re_from_aif : std_logic;
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signal rx_empty_from_aif : std_logic;
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signal rx_re_to_aif : std_logic;
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signal rx_data_from_aif : std_logic_vector(1+comm_width_g+data_width_g-1 downto 0);
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signal tx_msg_data_to_aif : std_logic_vector(1+comm_width_g+data_width_g-1 downto 0);
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signal tx_msg_empty_to_aif : std_logic;
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signal tx_msg_re_from_aif : std_logic;
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signal rx_msg_empty_from_aif : std_logic;
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signal rx_msg_re_to_aif : std_logic;
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signal rx_msg_data_from_aif : std_logic_vector(1+comm_width_g+data_width_g-1 downto 0);
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function log2 (
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constant value : integer)
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return integer is
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variable temp : integer := 1;
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variable counter : integer := 0;
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begin -- log2
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while temp < value loop
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temp := temp*2;
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counter := counter+1;
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end loop;
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return counter;
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end log2;
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begin -- structural
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-- Check generics
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assert (depth_0_g + depth_1_g > 0) report "Both fifo depths zero!" severity warning;
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-- Concurrent assignments
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Tie_High <= '1';
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Tie_Low <= '0';
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-- Splitting the data from fifo outputs
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av_0_out <= a_c_d_f0_output (1 + comm_width_g + data_width_g -1);
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comm_0_out <= a_c_d_f0_output (comm_width_g + data_width_g -1 downto data_width_g);
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data_0_out <= a_c_d_f0_output (data_width_g -1 downto 0);
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av_1_out <= a_c_d_f1_output (1+ comm_width_g + data_width_g -1);
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comm_1_out <= a_c_d_f1_output (comm_width_g + data_width_g -1 downto data_width_g);
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data_1_out <= a_c_d_f1_output (data_width_g -1 downto 0);
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multi : if fifo_sel_g = 0 generate
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-- synch multiclk
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Map_Fifo_0 : if depth_0_g > 0 generate
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Multiclk_Fifo_0 : multiclk_fifo
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|
|
generic map(
|
334 |
|
|
re_freq_g => re_freq_g,
|
335 |
|
|
we_freq_g => we_freq_g,
|
336 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
337 |
|
|
depth_g => depth_0_g
|
338 |
|
|
)
|
339 |
|
|
port map(
|
340 |
|
|
clk_re => clk_re,
|
341 |
|
|
clk_we => clk_we,
|
342 |
|
|
rst_n => rst_n,
|
343 |
|
|
data_in => a_c_d_to_f01,
|
344 |
|
|
we_in => we_to_f0,
|
345 |
|
|
full_out => full_from_f0,
|
346 |
|
|
one_p_out => one_p_from_f0,
|
347 |
|
|
|
348 |
|
|
re_in => re_0_in,
|
349 |
|
|
data_out => a_c_d_f0_output,
|
350 |
|
|
empty_out => empty_0_out,
|
351 |
|
|
one_d_out => one_d_0_out
|
352 |
|
|
);
|
353 |
|
|
end generate Map_Fifo_0;
|
354 |
|
|
|
355 |
|
|
Map_Fifo_1 : if depth_1_g > 0 generate
|
356 |
|
|
Multiclk_Fifo_1 : multiclk_fifo
|
357 |
|
|
generic map(
|
358 |
|
|
re_freq_g => re_freq_g,
|
359 |
|
|
we_freq_g => we_freq_g,
|
360 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
361 |
|
|
depth_g => depth_1_g
|
362 |
|
|
)
|
363 |
|
|
port map(
|
364 |
|
|
clk_re => clk_re,
|
365 |
|
|
clk_we => clk_we,
|
366 |
|
|
rst_n => rst_n,
|
367 |
|
|
|
368 |
|
|
data_in => a_c_d_to_f01,
|
369 |
|
|
we_in => we_to_f1,
|
370 |
|
|
one_p_out => one_p_from_f1,
|
371 |
|
|
full_out => full_from_f1,
|
372 |
|
|
|
373 |
|
|
re_in => re_1_in,
|
374 |
|
|
data_out => a_c_d_f1_output,
|
375 |
|
|
empty_out => empty_1_out,
|
376 |
|
|
one_d_out => one_d_1_out
|
377 |
|
|
);
|
378 |
|
|
end generate Map_Fifo_1;
|
379 |
|
|
|
380 |
|
|
end generate multi;
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
gals : if fifo_sel_g = 1 generate
|
384 |
|
|
-- GALS, may be used with fast synch
|
385 |
|
|
|
386 |
|
|
Map_Fifo_0 : if depth_0_g > 0 generate
|
387 |
|
|
|
388 |
|
|
aif_read_top_0 : aif_read_top
|
389 |
|
|
generic map (
|
390 |
|
|
data_width_g => 1 + comm_width_g + data_width_g
|
391 |
|
|
)
|
392 |
|
|
port map (
|
393 |
|
|
tx_clk => clk_we_pls,
|
394 |
|
|
tx_rst_n => rst_n,
|
395 |
|
|
tx_data_in => tx_data_to_aif,
|
396 |
|
|
tx_empty_in => tx_empty_to_aif,
|
397 |
|
|
tx_re_out => tx_re_from_aif,
|
398 |
|
|
|
399 |
|
|
rx_clk => clk_re, -- should be the agent clock...
|
400 |
|
|
rx_rst_n => rst_n,
|
401 |
|
|
rx_empty_out => empty_0_out,
|
402 |
|
|
rx_re_in => re_0_in,
|
403 |
|
|
rx_data_out => a_c_d_f0_output
|
404 |
|
|
);
|
405 |
|
|
|
406 |
|
|
|
407 |
|
|
Multiclk_Fifo_0 : multiclk_fifo
|
408 |
|
|
generic map(
|
409 |
|
|
re_freq_g => re_freq_g,
|
410 |
|
|
we_freq_g => we_freq_g,
|
411 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
412 |
|
|
depth_g => depth_0_g
|
413 |
|
|
)
|
414 |
|
|
port map(
|
415 |
|
|
clk_re => clk_we_pls,
|
416 |
|
|
clk_we => clk_we,
|
417 |
|
|
rst_n => rst_n,
|
418 |
|
|
data_in => a_c_d_to_f01,
|
419 |
|
|
we_in => we_to_f0,
|
420 |
|
|
full_out => full_from_f0,
|
421 |
|
|
one_p_out => one_p_from_f0, --- ???
|
422 |
|
|
|
423 |
|
|
re_in => tx_re_from_aif,
|
424 |
|
|
data_out => tx_data_to_aif,
|
425 |
|
|
empty_out => tx_empty_to_aif,
|
426 |
|
|
one_d_out => one_d_0_out -- ???
|
427 |
|
|
);
|
428 |
|
|
end generate Map_Fifo_0;
|
429 |
|
|
|
430 |
|
|
Map_Fifo_1 : if depth_1_g > 0 generate
|
431 |
|
|
|
432 |
|
|
aif_read_top_1 : aif_read_top
|
433 |
|
|
generic map (
|
434 |
|
|
data_width_g => 1 + comm_width_g + data_width_g
|
435 |
|
|
)
|
436 |
|
|
port map (
|
437 |
|
|
tx_clk => clk_we_pls,
|
438 |
|
|
tx_rst_n => rst_n,
|
439 |
|
|
tx_data_in => tx_msg_data_to_aif,
|
440 |
|
|
tx_empty_in => tx_msg_empty_to_aif,
|
441 |
|
|
tx_re_out => tx_msg_re_from_aif,
|
442 |
|
|
|
443 |
|
|
rx_clk => clk_re, -- should be the agent clock...
|
444 |
|
|
rx_rst_n => rst_n,
|
445 |
|
|
rx_empty_out => empty_1_out,
|
446 |
|
|
rx_re_in => re_1_in,
|
447 |
|
|
rx_data_out => a_c_d_f1_output
|
448 |
|
|
);
|
449 |
|
|
|
450 |
|
|
Multiclk_Fifo_1 : multiclk_fifo
|
451 |
|
|
generic map(
|
452 |
|
|
re_freq_g => re_freq_g,
|
453 |
|
|
we_freq_g => we_freq_g,
|
454 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
455 |
|
|
depth_g => depth_1_g
|
456 |
|
|
)
|
457 |
|
|
port map(
|
458 |
|
|
clk_re => clk_we_pls,
|
459 |
|
|
clk_we => clk_we,
|
460 |
|
|
rst_n => rst_n,
|
461 |
|
|
data_in => a_c_d_to_f01,
|
462 |
|
|
we_in => we_to_f1,
|
463 |
|
|
full_out => full_from_f1,
|
464 |
|
|
one_p_out => one_p_from_f1, --- ???
|
465 |
|
|
|
466 |
|
|
re_in => tx_msg_re_from_aif,
|
467 |
|
|
data_out => tx_msg_data_to_aif,
|
468 |
|
|
empty_out => tx_msg_empty_to_aif,
|
469 |
|
|
one_d_out => one_d_1_out -- ???
|
470 |
|
|
);
|
471 |
|
|
end generate Map_Fifo_1;
|
472 |
|
|
|
473 |
|
|
end generate gals;
|
474 |
|
|
|
475 |
|
|
|
476 |
|
|
gray : if fifo_sel_g = 2 generate
|
477 |
|
|
-- Gray FIFO
|
478 |
|
|
|
479 |
|
|
Map_Fifo_0 : if depth_0_g > 0 generate
|
480 |
|
|
cdc_fifo_0 : cdc_fifo
|
481 |
|
|
generic map (
|
482 |
|
|
READ_AHEAD_g => 1, -- this is the hibi style, look-ahead
|
483 |
|
|
SYNC_CLOCKS_g => 0, -- we use two flops
|
484 |
|
|
depth_log2_g => log2(depth_0_g),
|
485 |
|
|
dataw_g => 1 + comm_width_g + data_width_g)
|
486 |
|
|
port map (
|
487 |
|
|
rst_n => rst_n,
|
488 |
|
|
rd_clk => clk_re,
|
489 |
|
|
rd_en_in => re_0_in,
|
490 |
|
|
rd_empty_out => empty_0_out,
|
491 |
|
|
rd_one_d_out => one_d_0_out,
|
492 |
|
|
rd_data_out => a_c_d_f0_output,
|
493 |
|
|
|
494 |
|
|
wr_clk => clk_we,
|
495 |
|
|
wr_en_in => we_to_f0,
|
496 |
|
|
wr_full_out => full_from_f0,
|
497 |
|
|
wr_one_p_out => one_p_from_f0,
|
498 |
|
|
wr_data_in => a_c_d_to_f01
|
499 |
|
|
);
|
500 |
|
|
|
501 |
|
|
end generate Map_Fifo_0;
|
502 |
|
|
|
503 |
|
|
|
504 |
|
|
Map_Fifo_1 : if depth_1_g > 0 generate
|
505 |
|
|
cdc_fifo_1 : cdc_fifo
|
506 |
|
|
generic map (
|
507 |
|
|
READ_AHEAD_g => 1, -- this is the hibi style, look-ahead
|
508 |
|
|
SYNC_CLOCKS_g => 0, -- we use two flops
|
509 |
|
|
depth_log2_g => log2(depth_1_g),
|
510 |
|
|
dataw_g => 1 + comm_width_g + data_width_g
|
511 |
|
|
)
|
512 |
|
|
port map (
|
513 |
|
|
rst_n => rst_n,
|
514 |
|
|
rd_clk => clk_re,
|
515 |
|
|
rd_en_in => re_1_in,
|
516 |
|
|
rd_empty_out => empty_1_out,
|
517 |
|
|
rd_one_d_out => one_d_1_out,
|
518 |
|
|
rd_data_out => a_c_d_f1_output,
|
519 |
|
|
|
520 |
|
|
wr_clk => clk_we,
|
521 |
|
|
wr_en_in => we_to_f1,
|
522 |
|
|
wr_full_out => full_from_f1,
|
523 |
|
|
wr_one_p_out => one_p_from_f1,
|
524 |
|
|
wr_data_in => a_c_d_to_f01
|
525 |
|
|
);
|
526 |
|
|
end generate Map_Fifo_1;
|
527 |
|
|
|
528 |
|
|
end generate gray;
|
529 |
|
|
|
530 |
|
|
mixed : if fifo_sel_g = 3 generate
|
531 |
|
|
|
532 |
|
|
Map_Fifo_0 : if depth_0_g > 0 generate
|
533 |
|
|
Mixed_clk_Fifo_0 : mixed_clk_fifo
|
534 |
|
|
generic map(
|
535 |
|
|
re_faster_g => re_faster_c,
|
536 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
537 |
|
|
depth_g => depth_0_g
|
538 |
|
|
)
|
539 |
|
|
port map(
|
540 |
|
|
clk_re => clk_re,
|
541 |
|
|
clk_we => clk_we,
|
542 |
|
|
clk_ps_we => clk_we_pls,
|
543 |
|
|
clk_ps_re => clk_re_pls,
|
544 |
|
|
rst_n => rst_n,
|
545 |
|
|
|
546 |
|
|
data_in => a_c_d_to_f01,
|
547 |
|
|
we_in => we_to_f0,
|
548 |
|
|
full_out => full_from_f0,
|
549 |
|
|
one_p_out => one_p_from_f0,
|
550 |
|
|
|
551 |
|
|
re_in => re_0_in,
|
552 |
|
|
data_out => a_c_d_f0_output,
|
553 |
|
|
empty_out => empty_0_out,
|
554 |
|
|
one_d_out => one_d_0_out
|
555 |
|
|
);
|
556 |
|
|
end generate Map_Fifo_0;
|
557 |
|
|
|
558 |
|
|
Map_Fifo_1 : if depth_1_g > 0 generate
|
559 |
|
|
Mixed_clk_Fifo_1 : mixed_clk_fifo
|
560 |
|
|
generic map(
|
561 |
|
|
re_faster_g => re_faster_c,
|
562 |
|
|
data_width_g => 1 + comm_width_g + data_width_g,
|
563 |
|
|
depth_g => depth_1_g
|
564 |
|
|
)
|
565 |
|
|
port map(
|
566 |
|
|
clk_re => clk_re,
|
567 |
|
|
clk_we => clk_we,
|
568 |
|
|
clk_ps_we => clk_we_pls,
|
569 |
|
|
clk_ps_re => clk_re_pls,
|
570 |
|
|
rst_n => rst_n,
|
571 |
|
|
|
572 |
|
|
data_in => a_c_d_to_f01,
|
573 |
|
|
we_in => we_to_f1,
|
574 |
|
|
one_p_out => one_p_from_f1,
|
575 |
|
|
full_out => full_from_f1,
|
576 |
|
|
|
577 |
|
|
re_in => re_1_in,
|
578 |
|
|
data_out => a_c_d_f1_output,
|
579 |
|
|
empty_out => empty_1_out,
|
580 |
|
|
one_d_out => one_d_1_out
|
581 |
|
|
);
|
582 |
|
|
end generate Map_Fifo_1;
|
583 |
|
|
|
584 |
|
|
end generate mixed;
|
585 |
|
|
|
586 |
|
|
|
587 |
|
|
Not_Map_Fifo_0 : if depth_0_g = 0 generate
|
588 |
|
|
|
589 |
|
|
assert false report "Do not map fifo 0 (depth=0)" severity note;
|
590 |
|
|
|
591 |
|
|
-- Fifo #0 and demux does not exist!
|
592 |
|
|
a_c_d_f0_output <= (others => '0');
|
593 |
|
|
empty_0_out <= Tie_High;
|
594 |
|
|
one_d_0_out <= Tie_Low;
|
595 |
|
|
full_from_f0 <= Tie_High;
|
596 |
|
|
one_p_from_f0 <= Tie_Low;
|
597 |
|
|
we_to_f0 <= Tie_Low;
|
598 |
|
|
|
599 |
|
|
-- Connect the other fifo (#1) straight to the outputs/inputs
|
600 |
|
|
one_p_out <= one_p_from_f1;
|
601 |
|
|
full_out <= full_from_f1;
|
602 |
|
|
|
603 |
|
|
-- replace with concatenation?
|
604 |
|
|
a_c_d_to_f01(comm_width_g + data_width_g) <= av_in;
|
605 |
|
|
a_c_d_to_f01(comm_width_g + data_width_g-1 downto data_width_g) <= comm_in;
|
606 |
|
|
a_c_d_to_f01(data_width_g-1 downto 0) <= data_in;
|
607 |
|
|
|
608 |
|
|
we_to_f1 <= we_in;
|
609 |
|
|
end generate Not_Map_Fifo_0;
|
610 |
|
|
|
611 |
|
|
Not_Map_Fifo_1 : if depth_1_g = 0 generate
|
612 |
|
|
assert false report "Do not map fifo 1 (depth_g = 0)" severity note;
|
613 |
|
|
-- Fifo #1 and demux does not exist!
|
614 |
|
|
a_c_d_f1_output <= (others => '0');
|
615 |
|
|
empty_1_out <= Tie_High;
|
616 |
|
|
one_d_1_out <= Tie_Low;
|
617 |
|
|
full_from_f1 <= Tie_High;
|
618 |
|
|
one_p_from_f1 <= Tie_Low;
|
619 |
|
|
we_to_f1 <= Tie_Low;
|
620 |
|
|
|
621 |
|
|
-- Connect the other fifo (#0) straight to the outputs/inputs
|
622 |
|
|
one_p_out <= one_p_from_f0;
|
623 |
|
|
full_out <= full_from_f0;
|
624 |
|
|
|
625 |
|
|
-- replace with concatenation?
|
626 |
|
|
a_c_d_to_f01(1 + comm_width_g + data_width_g -1) <= av_in;
|
627 |
|
|
a_c_d_to_f01(comm_width_g + data_width_g -1 downto data_width_g) <= comm_in;
|
628 |
|
|
a_c_d_to_f01(data_width_g -1 downto 0) <= data_in;
|
629 |
|
|
|
630 |
|
|
|
631 |
|
|
|
632 |
|
|
we_to_f0 <= we_in;
|
633 |
|
|
|
634 |
|
|
end generate Not_Map_Fifo_1;
|
635 |
|
|
|
636 |
|
|
|
637 |
|
|
Map_Demux : if depth_0_g > 0 and depth_1_g > 0 generate
|
638 |
|
|
-- Demultiplexer is needed only if two fifos are used
|
639 |
|
|
DEMUX_01 : fifo_demux_wr
|
640 |
|
|
generic map(
|
641 |
|
|
data_width_g => data_width_g,
|
642 |
|
|
comm_width_g => comm_width_g
|
643 |
|
|
)
|
644 |
|
|
port map(
|
645 |
|
|
|
646 |
|
|
data_in => data_xf_demux,
|
647 |
|
|
comm_in => comm_xf_demux,
|
648 |
|
|
av_in => av_xf_demux,
|
649 |
|
|
we_in => we_xf_demux,
|
650 |
|
|
full_out => full_demux_xf,
|
651 |
|
|
--one_p_out => one_p_demux_xf,
|
652 |
|
|
|
653 |
|
|
|
654 |
|
|
av_out => a_c_d_to_f01 (1 + comm_width_g + data_width_g -1),
|
655 |
|
|
comm_out => a_c_d_to_f01 (comm_width_g + data_width_g -1 downto data_width_g),
|
656 |
|
|
data_out => a_c_d_to_f01 (data_width_g -1 downto 0),
|
657 |
|
|
|
658 |
|
|
we_0_out => we_to_f0,
|
659 |
|
|
we_1_out => we_to_f1,
|
660 |
|
|
full_0_in => full_from_f0,
|
661 |
|
|
full_1_in => full_from_f1,
|
662 |
|
|
one_p_0_in => one_p_from_f0,
|
663 |
|
|
one_p_1_in => one_p_from_f1
|
664 |
|
|
);
|
665 |
|
|
end generate Map_Demux;
|
666 |
|
|
|
667 |
|
|
|
668 |
|
|
Map_xtrafifo : if depth_0_g > 0 and depth_1_g > 0 generate
|
669 |
|
|
-- Xtra fifo is needed only if two fifos (and demux) are used
|
670 |
|
|
-- xtra_in_fifo : multiclk_fifo
|
671 |
|
|
xtra_in_fifo : fifo
|
672 |
|
|
-- regular FIFO
|
673 |
|
|
generic map (
|
674 |
|
|
data_width_g => 1+ comm_width_g + data_width_g,
|
675 |
|
|
depth_g => 3
|
676 |
|
|
)
|
677 |
|
|
port map(
|
678 |
|
|
clk => clk_we,
|
679 |
|
|
rst_n => rst_n,
|
680 |
|
|
|
681 |
|
|
data_in => a_c_d_input_xf,
|
682 |
|
|
we_in => we_in,
|
683 |
|
|
one_p_out => one_p_out,
|
684 |
|
|
full_out => full_out,
|
685 |
|
|
|
686 |
|
|
re_in => re_demux_xf,
|
687 |
|
|
data_out => a_c_d_xf_demux,
|
688 |
|
|
empty_out => empty_xf_demux --,
|
689 |
|
|
--one_d_out => one_d_1_out
|
690 |
|
|
);
|
691 |
|
|
|
692 |
|
|
-- Handshaking between xtra fifo and demux
|
693 |
|
|
we_xf_demux <= not empty_xf_demux;
|
694 |
|
|
re_demux_xf <= not full_demux_xf;
|
695 |
|
|
|
696 |
|
|
-- Split extra fifo output before feeding it to demux
|
697 |
|
|
av_xf_demux <= a_c_d_xf_demux (1 + comm_width_g + data_width_g -1);
|
698 |
|
|
comm_xf_demux <= a_c_d_xf_demux (comm_width_g + data_width_g -1 downto data_width_g);
|
699 |
|
|
data_xf_demux <= a_c_d_xf_demux (data_width_g -1 downto 0);
|
700 |
|
|
|
701 |
|
|
-- Join inputs for xtra fifo
|
702 |
|
|
a_c_d_input_xf <= av_in & comm_in & data_in;
|
703 |
|
|
|
704 |
|
|
end generate Map_xtrafifo;
|
705 |
|
|
|
706 |
|
|
end structural;
|
707 |
|
|
|
708 |
|
|
|
709 |
|
|
|
710 |
|
|
|