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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Dynamic arbitration algorith, lfsr+lut
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-- Project :
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-------------------------------------------------------------------------------
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-- File : dyn_arb.vhd
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-- Author :
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-- Created : 22.05.2006
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-- Last update: 2009-04-08
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-- Description: dynamic arbitration algorithm
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-------------------------------------------------------------------------------
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-- Copyright (c) 2006
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 22.05.2006 1.0 AK Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all; poistin 2009-04-06 ES
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all; -- ES 2009-04-06
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entity dyn_arb is
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generic (
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id_width_g : integer := 0;
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n_agents_g : integer := 0);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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bus_lock_in : in std_logic;
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-- incr_agent_in : in std_logic_vector(n_agents_g-1 downto 0);
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arb_agent_out : out std_logic_vector(id_width_g-1 downto 0) -- values 1..n
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);
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end dyn_arb;
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architecture rtl of dyn_arb is
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component lfsr
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generic (
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width_g : integer range 1 to 36);
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port (
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rst_n : in std_logic;
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enable_in : in std_logic;
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q_out : out std_logic_vector(width_g-1 downto 0);
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clk : in std_logic);
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end component;
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constant qos_slots_c : integer := 3; -- how many fixed slots per agent
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-- Signals for Linear Feedback Shift Register (LFSR) that generates (pseudo)
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-- random numbers
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constant lfsr_width_c : integer := 8; -- note! 6 bits only used!
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constant lut_size_c : integer := 2**(lfsr_width_c-1);
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signal q_from_lfsr : std_logic_vector(lfsr_width_c-1 downto 0); --(pseudo-)rand value
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signal enable_lfsr_r : std_logic;
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-- Array that stores the "lottery tickets"
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type turn_lut_array is array (lut_size_c-1 downto 0) of std_logic_vector(id_width_g-1 downto 0);
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-- type turn_lut_array is array (2**(lfsr_width_c-1)-1 downto 0) of std_logic_vector(id_width_g-1 downto 0);
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signal adaptive_lut_r : turn_lut_array;
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signal arb_agent : std_logic_vector(id_width_g-1 downto 0); -- winner
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signal out_was_r : std_logic_vector(id_width_g-1 downto 0);
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signal prev_lock_r : std_logic;
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-- ES 2009-04-06
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-- Calculate LUT statistics for debug. Simulation purposes only.
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-- Modelsim may obtimize this away, so you must statt simulation with
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-- optimizations disabled : vsim -novopt tb_hibiv2_lat etc.
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type ticket_count_table_type is array (n_agents_g+1-1 downto 0) of integer;
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signal ticket_count_table_r : ticket_count_table_type;
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begin -- rtl
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arb_agent_out <= arb_agent;
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enable_lfsr_r <= not bus_lock_in;
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assert lut_size_c >= n_agents_g * qos_slots_c report "Too mnay qos slots" severity failure;
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main : process (clk, rst_n)
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begin -- process main
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if rst_n = '0' then -- asynchronous reset (active low)
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dyn_slots: for i in 0 to lut_size_c-(n_agents_g * qos_slots_c)-1 loop
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adaptive_lut_r(i) <= std_logic_vector(to_unsigned ((i mod n_agents_g) +1, id_width_g)); -- 2009-04-06
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end loop dyn_slots;
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qos : for i in lut_size_c-(n_agents_g * qos_slots_c) to lut_size_c-1 loop
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adaptive_lut_r(i) <= std_logic_vector(to_unsigned ((i mod n_agents_g)+1, id_width_g));
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end loop qos;
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prev_lock_r <= '0';
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out_was_r <= (others => '0'); -- 2009-04-08
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elsif clk'event and clk = '1' then -- rising clock edge
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adaptive_lut_r <= adaptive_lut_r;
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out_was_r <= arb_agent; -- 2009-04-08
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out_was_r <= adaptive_lut_r(conv_integer(q_from_lfsr(lfsr_width_c-1 downto 1)));
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-- Update the LUT when owner uses its turn, i.e. when lock goes 0 -> 1
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-- Updating inserts owner ID to slot(0) and shift the dynamic slots left
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-- (towards bigger indices) by 1.
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if bus_lock_in = '0' then
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prev_lock_r <= '0';
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else
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prev_lock_r <= '1';
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if prev_lock_r = '0' then
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for i in 0 to lut_size_c-(n_agents_g*qos_slots_c)-2 loop
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-- for i in 0 to 2**(lfsr_width_c-1)-(n_agents_g*qos_slots_c)-2 loop
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adaptive_lut_r(i+1) <= adaptive_lut_r(i);
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end loop; -- i
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adaptive_lut_r(0) <= out_was_r;
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end if;
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end if;
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end if;
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end process main;
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arb_agent <= adaptive_lut_r(conv_integer(q_from_lfsr(lfsr_width_c-1 downto 1)));
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-- Generate random numbers
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lfsr_1 : lfsr
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generic map (
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width_g => lfsr_width_c
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)
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port map (
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rst_n => rst_n,
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enable_in => enable_lfsr_r,
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q_out => q_from_lfsr,
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clk => clk);
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-- ES 2009-04-06 A process for debugging
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count_tickets : process (clk, rst_n)
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variable ticket_owner_v : integer := 0;
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variable ticket_count_table_v : ticket_count_table_type;
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begin -- process count_tickets
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if rst_n = '0' then -- asynchronous reset (active low)
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ticket_count_table_r <= (others => 0);
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elsif clk'event and clk = '1' then -- rising clock edge
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ticket_count_table_v := (others => 0);
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for i in 0 to lut_size_c-1 loop
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ticket_owner_v := to_integer(signed(adaptive_lut_r(i)));
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ticket_count_table_v (ticket_owner_v) := ticket_count_table_v (ticket_owner_v) +1;
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end loop; -- i
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ticket_count_table_r <= ticket_count_table_v;
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end if;
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end process count_tickets;
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end rtl;
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