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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [2.0/] [vhd/] [hibi_wrapper_r4.vhd] - Blame information for rev 145

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1 145 lanttu
-------------------------------------------------------------------------------
2
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
3
--
4
-- This source file may be used and distributed without
5
-- restriction provided that this copyright statement is not
6
-- removed from the file and that any derivative work contains
7
-- the original copyright notice and the associated disclaimer.
8
--
9
-- This source file is free software; you can redistribute it
10
-- and/or modify it under the terms of the GNU Lesser General
11
-- Public License as published by the Free Software Foundation;
12
-- either version 2.1 of the License, or (at your option) any
13
-- later version.
14
--
15
-- This source is distributed in the hope that it will be
16
-- useful, but WITHOUT ANY WARRANTY; without even the implied
17
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
18
-- PURPOSE.  See the GNU Lesser General Public License for more
19
-- details.
20
--
21
-- You should have received a copy of the GNU Lesser General
22
-- Public License along with this source; if not, download it
23
-- from http://www.opencores.org/lgpl.shtml
24
-------------------------------------------------------------------------------
25
-------------------------------------------------------------------------------
26
-- File        : hibi_wrapper_r4.vhdl
27
-- Description : hibi bus wrapper. 
28
--               only one tx/rx fifo visible in the interface.
29
--               mux directs the data to right fifo depending on the command.
30
--               address is indicated by address valid-signal
31
-- Author      : Ari Kulmala
32
-- e-mail      : ari.kulmala@tut.fi
33
-- Design      : Do not use term design when you mean system
34
-- Date        : 16.8.2004
35
-- Modified    : 
36
-- 04.01.2005 AK Names changed.
37
-- 
38
--
39
-- 28.02.2005   ES cfg_rom_en_g removed, cfg_re and cfg_we added
40
-- 13.01.2006   AK finished mappings when either of fifos has depth of 0.
41
-------------------------------------------------------------------------------
42
library ieee;
43
use ieee.std_logic_1164.all;
44
use ieee.std_logic_arith.all;
45
use ieee.std_logic_unsigned.all;
46
 
47
 
48
entity hibi_wrapper_r4 is
49
generic (
50
    -- Note: n_   = number of,
51
    --       lte  = less than or equal,
52
    --       gte  = greater than or equal 
53
 
54
    -- Structural settings.
55
    --  All widths are given in bits
56
    addr_width_g    : integer := 32; -- lte data_width 
57
    data_width_g    : integer := 32;
58
    comm_width_g    : integer := 3;  -- practically always 3
59
    counter_width_g : integer := 7;  -- gte (n_agents, max_send...) 
60
    debug_width_g  : integer := 0;   -- for special monitors
61
 
62
    --  All FIFO depths are given in words
63
    --  Allowed values 0,2,3... words.
64
    --  Prefix msg refers to hi-prior data
65
    rx_fifo_depth_g     : integer := 5;
66
    tx_fifo_depth_g     : integer := 5;
67
    rx_msg_fifo_depth_g : integer := 5;
68
    tx_msg_fifo_depth_g : integer := 5;
69
 
70
    --  Clocking and synchronization
71
    -- fifo_sel: 0 synch multiclk,         1 basic GALS,
72
    --           2 Gray FIFO (depth=2^n!), 3 mixed clock pausible
73
    fifo_sel_g : integer := 0; -- use 0 for synchronous systems
74
    --  E.g. Synch_multiclk FIFOs must know the ratio of frequencies
75
    rel_agent_freq_g : integer := 1;
76
    rel_bus_freq_g   : integer := 1;
77
 
78
 
79
    -- Functional: addressing settings
80
    addr_g        : integer := 46; -- unique for each wrapper
81
    inv_addr_en_g : integer := 0;  -- only for bridges
82
    multicast_en_g : integer := 0; -- enable special addressing
83
 
84
    -- Functional: arbitration
85
    --  arb_type 0 round-robin, 1 priority, 2 combined, 3 DAA.
86
        --  TDMA is enabled by setting n_time_slots > 0
87
    --  Ensure that all wrappers in a segment agree on arb_type,
88
    --  n_agents, and n_slots. Max_send can be wrapper-specific.
89
    n_agents_g       : integer := 4;  -- within one segment
90
    prior_g          : integer := 2;  -- lte n_agents
91
    max_send_g       : integer := 50; -- in words, 0 means unlimited
92
    n_time_slots_g   : integer := 0;  -- for TDMA
93
    arb_type_g       : integer := 0;
94
    keep_slot_g      : integer := 1;  -- for TDMA
95
 
96
    -- Func/Stuctural: (Run-time re)configuration memory
97
    id_g          : integer := 5;  -- used instead of addr in recfg
98
    id_width_g    : integer := 4;  -- gte(log2(id_g))
99
    base_id_g     : integer := 5;  -- only for bridges
100
    cfg_re_g      : integer := 0;  -- enable reading config
101
    cfg_we_g      : integer := 0;  -- enable writing config
102
    n_extra_params_g : integer := 0; -- app-specific registers
103
    --  Having multiple pages allows fast reconfig
104
    n_cfg_pages_g : integer := 1
105
    --  Note that cfg memory initialization is done with separate
106
    --  package if you have many time slots or configuration pages
107
 
108
    );
109
  port (
110
    bus_clk          : in std_logic;
111
    agent_clk        : in std_logic;
112
    -- pulsed clocks as used in pausible clock scheme (fifo 3)
113
    -- IF fifo 1 and fast synch is used, sync clocks is used as the
114
    -- HIBI synch clock 
115
    bus_sync_clk     : in std_logic;
116
    agent_sync_clk   : in std_logic;
117
    rst_n            : in std_logic;
118
    bus_comm_in      : in std_logic_vector (comm_width_g-1 downto 0);
119
    bus_data_in      : in std_logic_vector (data_width_g-1 downto 0);
120
    bus_full_in      : in std_logic;
121
    bus_lock_in      : in std_logic;
122
    bus_av_in        : in std_logic;
123
 
124
    agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
125
    agent_data_in : in std_logic_vector (data_width_g-1 downto 0);
126
    agent_av_in   : in std_logic;
127
    agent_we_in   : in std_logic;
128
    agent_re_in   : in std_logic;
129
 
130
    bus_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
131
    bus_data_out : out std_logic_vector (data_width_g-1 downto 0);
132
    bus_full_out : out std_logic;
133
    bus_lock_out : out std_logic;
134
    bus_av_out   : out std_logic;
135
 
136
    agent_comm_out  : out std_logic_vector (comm_width_g-1 downto 0);
137
    agent_data_out  : out std_logic_vector (data_width_g-1 downto 0);
138
    agent_av_out    : out std_logic;
139
    agent_full_out  : out std_logic;
140
    agent_one_p_out : out std_logic;
141
    agent_empty_out : out std_logic;
142
    agent_one_d_out : out std_logic
143
 
144
    -- synthesis translate_off
145
    -- pragma translate_off
146
    ;
147
    debug_out : out std_logic_vector(debug_width_g-1 downto 0);
148
    debug_in : in std_logic_vector(debug_width_g-1 downto 0)
149
    -- pragma translate_on
150
    -- synthesis translate_on
151
    );
152
end hibi_wrapper_r4;
153
 
154
 
155
 
156
 
157
architecture structural of hibi_wrapper_r4 is
158
 
159
 
160
  -- structure
161
  --                           hibi_wrapper_r4
162
  --              ########################################################
163
  --              #                                                      #
164
  -- ip_input  => #  => fifo_demux_wr => hibiv.2  # => bus_output
165
  --              #            (dw)                  #
166
  --              #                                                      #
167
  --              #                                                      #
168
  -- ip_output <= # <=  fifo_mux_rd <=  hibiv.2   # <= bus_input
169
  --              #           (mr)                  #
170
  --              #                                 #
171
  --              #                                 #
172
  --              ########################################################
173
  --
174
  --
175
  -- signal names  =>              xxx_mw_dw               xxx_dw_h
176
  --               <=              xxx_mr_dr               xxx_h_mr
177
  --               
178
 
179
  -- signals between fifo_demux_wr and hibi wrapper
180
  signal data_dw_h    : std_logic_vector (data_width_g-1 downto 0);
181
  signal comm_dw_h    : std_logic_vector (comm_width_g-1 downto 0);
182
  signal av_dw_h      : std_logic;
183
  signal we_0_dw_h    : std_logic;
184
  signal we_1_dw_h    : std_logic;
185
  signal full_0_h_dw  : std_logic;      --
186
  signal full_1_h_dw  : std_logic;
187
  signal one_p_0_h_dw : std_logic;
188
  signal one_p_1_h_dw : std_logic;
189
 
190
  -- signals between hibi wrapper and fifo_demux_wr
191
  signal data_0_h_mr  : std_logic_vector (data_width_g-1 downto 0);
192
  signal comm_0_h_mr  : std_logic_vector (comm_width_g-1 downto 0);
193
  signal data_1_h_mr  : std_logic_vector (data_width_g-1 downto 0);
194
  signal comm_1_h_mr  : std_logic_vector (comm_width_g-1 downto 0);
195
  signal av_0_h_mr    : std_logic;
196
  signal av_1_h_mr    : std_logic;
197
  signal re_0_mr_h    : std_logic;
198
  signal re_1_mr_h    : std_logic;
199
  signal empty_0_h_mr : std_logic;
200
  signal empty_1_h_mr : std_logic;
201
  signal one_d_0_h_mr : std_logic;
202
  signal one_d_1_h_mr : std_logic;
203
 
204
  -- takes addr and data sequentially and writes them
205
  -- into one of two fifos depending on command
206
  component fifo_demux_wr
207
    generic (
208
      data_width_g : integer := 0;
209
      comm_width_g : integer := 0
210
      );
211
    port (
212
      -- 13.04 fully asynchronous!
213
      data_in    : in  std_logic_vector (data_width_g-1 downto 0);
214
      av_in      : in  std_logic;
215
      comm_in    : in  std_logic_vector (comm_width_g-1 downto 0);
216
      we_in      : in  std_logic;
217
      one_p_out  : out std_logic;
218
      full_out   : out std_logic;
219
      -- data/comm/av conencted to both fifos
220
      -- distinction made with we!
221
      data_out   : out std_logic_vector (data_width_g-1 downto 0);
222
      comm_out   : out std_logic_vector (comm_width_g-1 downto 0);
223
      av_out     : out std_logic;
224
      we_0_out   : out std_logic;
225
      we_1_out   : out std_logic;
226
      full_0_in  : in  std_logic;
227
      full_1_in  : in  std_logic;
228
      one_p_0_in : in  std_logic;
229
      one_p_1_in : in  std_logic
230
      );
231
  end component;  --fifo_demux_wr;
232
 
233
  -- reads to fifos and
234
  -- writes addr and data sequentially forward depending on command
235
  component fifo_mux_rd
236
    generic (
237
      data_width_g : integer := 0;
238
      comm_width_g : integer := 0
239
      );
240
    port (
241
      clk   : in std_logic;
242
      rst_n : in std_logic;
243
 
244
      data_0_in  : in  std_logic_vector (data_width_g-1 downto 0);
245
      comm_0_in  : in  std_logic_vector (comm_width_g-1 downto 0);
246
      av_0_in    : in  std_logic;
247
      one_d_0_in : in  std_logic;
248
      empty_0_in : in  std_logic;
249
      re_0_out   : out std_logic;
250
 
251
      data_1_in  : in  std_logic_vector (data_width_g-1 downto 0);
252
      comm_1_in  : in  std_logic_vector (comm_width_g-1 downto 0);
253
      av_1_in    : in  std_logic;
254
      one_d_1_in : in  std_logic;
255
      empty_1_in : in  std_logic;
256
      re_1_out   : out std_logic;
257
      re_in      : in  std_logic;
258
 
259
      data_out  : out std_logic_vector (data_width_g-1 downto 0);
260
      comm_out  : out std_logic_vector (comm_width_g-1 downto 0);
261
      av_out    : out std_logic;
262
      one_d_out : out std_logic;
263
      empty_out : out std_logic
264
      );
265
  end component;  --fifo_mux_rd;
266
 
267
begin
268
 
269
  hibi_wra : entity work.hibi_wrapper_r1
270
    --hibi_wra : hibi_wrapper
271
    generic map(
272
      id_g      => id_g,
273
      base_id_g => base_id_g,
274
 
275
      id_width_g      => id_width_g,
276
      addr_width_g    => addr_width_g,
277
      data_width_g    => data_width_g,
278
      comm_width_g    => comm_width_g,
279
      counter_width_g => counter_width_g,
280
 
281
      rel_bus_freq_g   => rel_bus_freq_g,
282
      rel_agent_freq_g => rel_agent_freq_g,
283
 
284
      rx_fifo_depth_g     => rx_fifo_depth_g,
285
      rx_msg_fifo_depth_g => rx_msg_fifo_depth_g,
286
      tx_fifo_depth_g     => tx_fifo_depth_g,
287
      tx_msg_fifo_depth_g => tx_msg_fifo_depth_g,
288
 
289
      fifo_sel_g => fifo_sel_g,
290
      arb_type_g => arb_type_g,
291
 
292
      addr_g        => addr_g,
293
      prior_g       => prior_g,
294
      inv_addr_en_g => inv_addr_en_g,
295
 
296
      max_send_g       => max_send_g,
297
      n_agents_g       => n_agents_g,
298
      n_cfg_pages_g    => n_cfg_pages_g,
299
      n_time_slots_g   => n_time_slots_g,
300
      keep_slot_g      => keep_slot_g,
301
      n_extra_params_g => n_extra_params_g,
302
      multicast_en_g   => multicast_en_g,
303
      cfg_re_g         => cfg_re_g,
304
      cfg_we_g         => cfg_we_g,
305
      debug_width_g    => debug_width_g
306
      )
307
    port map(
308
      bus_clk          => bus_clk,
309
      agent_clk        => agent_clk,
310
      bus_sync_clk     => bus_sync_clk,
311
      agent_sync_clk   => agent_sync_clk,
312
      rst_n            => rst_n,
313
 
314
      bus_comm_in => bus_comm_in,
315
      bus_data_in => bus_data_in,
316
      bus_full_in => bus_full_in,
317
      bus_lock_in => bus_lock_in,
318
      bus_av_in   => bus_av_in,
319
 
320
      agent_av_in     => av_dw_h,
321
      agent_data_in   => data_dw_h,
322
      agent_comm_in   => comm_dw_h,
323
      agent_we_in     => we_1_dw_h,
324
      agent_full_out  => full_1_h_dw,
325
      agent_one_p_out => one_p_1_h_dw,
326
 
327
      agent_msg_av_in     => agent_av_in,
328
      agent_msg_data_in   => agent_data_in,
329
      agent_msg_comm_in   => agent_comm_in,
330
      agent_msg_we_in     => we_0_dw_h,
331
      agent_msg_full_out  => full_0_h_dw,
332
      agent_msg_one_p_out => one_p_0_h_dw,
333
 
334
      bus_av_out   => bus_av_out,
335
      bus_comm_out => bus_comm_out,
336
      bus_data_out => bus_data_out,
337
      bus_full_out => bus_full_out,
338
      bus_lock_out => bus_lock_out,
339
 
340
      agent_av_out    => av_1_h_mr,
341
      agent_data_out  => data_1_h_mr,
342
      agent_comm_out  => comm_1_h_mr,
343
      agent_re_in     => re_1_mr_h,
344
      agent_empty_out => empty_1_h_mr,
345
      agent_one_d_out => one_d_1_h_mr,
346
 
347
      agent_msg_av_out    => av_0_h_mr,
348
      agent_msg_data_out  => data_0_h_mr,
349
      agent_msg_comm_out  => comm_0_h_mr,
350
      agent_msg_re_in     => re_0_mr_h,
351
      agent_msg_empty_out => empty_0_h_mr,
352
      agent_msg_one_d_out => one_d_0_h_mr
353
 
354
      --synthesis translate_off
355
      ,
356
      debug_in => debug_in,
357
      debug_out => debug_out
358
      --synthesis translate_on
359
      );
360
 
361
 
362
 
363
 
364
 
365
  -- if-generate added,  04.05.2005 Es
366
  map_mux_rd : if rx_fifo_depth_g > 0 and rx_msg_fifo_depth_g > 0 generate
367
 
368
    -- reads to fifos and
369
    -- writes addr and data sequentially forward depending on command
370
    -- reads data from hibi wrapper.
371
    mr : fifo_mux_rd
372
      generic map(
373
        data_width_g => data_width_g,
374
        comm_width_g => comm_width_g
375
        )
376
      port map(
377
        clk   => agent_clk,
378
        rst_n => rst_n,
379
 
380
        av_0_in    => av_0_h_mr,
381
        data_0_in  => data_0_h_mr,
382
        comm_0_in  => comm_0_h_mr,
383
        one_d_0_in => one_d_0_h_mr,
384
        empty_0_in => empty_0_h_mr,
385
        re_0_out   => re_0_mr_h,
386
 
387
        av_1_in    => av_1_h_mr,
388
        data_1_in  => data_1_h_mr,
389
        comm_1_in  => comm_1_h_mr,
390
        one_d_1_in => one_d_1_h_mr,
391
        empty_1_in => empty_1_h_mr,
392
        re_1_out   => re_1_mr_h,
393
        re_in      => agent_re_in,
394
 
395
        av_out    => agent_av_out,
396
        data_out  => agent_data_out,
397
        comm_out  => agent_comm_out,
398
        one_d_out => agent_one_d_out,
399
        empty_out => agent_empty_out
400
        );
401
 
402
    -- takes addr and data sequentially and writes them
403
    -- into one of two fifos depending on command
404
    -- gets data from ip and writes it to hibi wrapper
405
    dw : fifo_demux_wr
406
      generic map(
407
        data_width_g => data_width_g,
408
        comm_width_g => comm_width_g
409
        )
410
      port map(
411
        -- 13.04 fully asynchronous!
412
        data_in    => agent_data_in,
413
        av_in      => agent_av_in,
414
        comm_in    => agent_comm_in,
415
        we_in      => agent_we_in,
416
        one_p_out  => agent_one_p_out,
417
        full_out   => agent_full_out,
418
        -- data/comm/av connected to both fifos
419
        -- distinction made with we!
420
        av_out     => av_dw_h,
421
        data_out   => data_dw_h,
422
        comm_out   => comm_dw_h,
423
        we_0_out   => we_0_dw_h,
424
        we_1_out   => we_1_dw_h,
425
        full_0_in  => full_0_h_dw,
426
        full_1_in  => full_1_h_dw,
427
        one_p_0_in => one_p_0_h_dw,
428
        one_p_1_in => one_p_1_h_dw
429
        );
430
 
431
  end generate map_mux_rd;
432
 
433
  not_map_fifo_low : if rx_fifo_depth_g = 0 generate
434
 
435
    -- now map the msg fifo signals straight to the output
436
    agent_av_out    <= av_0_h_mr;
437
    agent_data_out  <= data_0_h_mr;
438
    agent_comm_out  <= comm_0_h_mr;
439
    agent_one_d_out <= one_d_0_h_mr;
440
    agent_empty_out <= empty_0_h_mr;
441
    re_0_mr_h       <= agent_re_in;
442
 
443
    agent_full_out  <= full_0_h_dw;
444
    agent_one_p_out <= one_p_0_h_dw;
445
    av_dw_h         <= agent_av_in;
446
    data_dw_h       <= agent_data_in;
447
    comm_dw_h       <= agent_comm_in;
448
    we_0_dw_h       <= agent_we_in;
449
 
450
--    agent_av_out    <= av_0_h_mr or av_1_h_mr;
451
--    agent_data_out  <= data_0_h_mr or data_1_h_mr;
452
--    agent_comm_out  <= comm_0_h_mr or comm_1_h_mr;
453
--    agent_one_d_out <= one_d_0_h_mr or one_d_1_h_mr;
454
--    agent_empty_out <= empty_0_h_mr and empty_1_h_mr;  -- note : AND instead of OR
455
 
456
--    re_1_mr_h <= agent_re_in;
457
 
458
  end generate not_map_fifo_low;
459
 
460
 
461
  not_map_fifo_high : if rx_msg_fifo_depth_g = 0 generate
462
 
463
    -- now map the msg fifo signals straight to the output
464
    agent_av_out    <= av_1_h_mr;
465
    agent_data_out  <= data_1_h_mr;
466
    agent_comm_out  <= comm_1_h_mr;
467
    agent_one_d_out <= one_d_1_h_mr;
468
    agent_empty_out <= empty_1_h_mr;
469
    re_1_mr_h       <= agent_re_in;
470
 
471
    agent_full_out  <= full_1_h_dw;
472
    agent_one_p_out <= one_p_1_h_dw;
473
    av_dw_h         <= agent_av_in;
474
    data_dw_h       <= agent_data_in;
475
    comm_dw_h       <= agent_comm_in;
476
    we_1_dw_h       <= agent_we_in;
477
 
478
  end generate not_map_fifo_high;
479
 
480
end structural;

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