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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [2.0/] [vhd/] [transmitter.vhd] - Blame information for rev 145

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1 145 lanttu
-------------------------------------------------------------------------------
2
-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
3
--
4
-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE.  See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File        : transmitter.vhdl
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-- Description : 
28
--               
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-- Author      : Erno Salminen
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-- e-mail      : erno.salminen@tut.fi
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-- Project     : huuhaa
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-- Design      : Do not use term design when you mean system
33
-- Date        : 23.07.2002
34
-- Modified    : 
35
--
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-- 12.04.03     Total_amount, Addr_Amount input ports
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--              and Fifo_Depth generic removed from tx_control
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-- 13.04        message stuff removed, es
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--
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-- 15.12.04     ES: names changed
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-- 31.01.05     ES addr_width_g in bits
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-- 07.02.05     ES new generic cfg_re_g
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-- 28.02.05     ES generic cfg_we and cfg_re added, cfg_rom_en_g removed
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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50
 
51
entity transmitter is
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53
  generic (
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    id_g            : integer := 5;
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    base_id_g       : integer := 5;
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    addr_g          : integer := 46;
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    id_width_g      : integer := 4;
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    data_width_g    : integer := 32;    -- in bits
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    addr_width_g    : integer := 32;    -- in bits!
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    comm_width_g    : integer := 3;
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    counter_width_g : integer := 8;
62
 
63
    cfg_addr_width_g : integer := 7;
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    prior_g       : integer := 2;
65
    inv_addr_en_g : integer := 0;
66
    max_send_g    : integer := 50;
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    arb_type_g    : integer := 0;
68
 
69
    n_agents_g       :    integer := 4;
70
    n_cfg_pages_g    :    integer := 1;
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    n_time_slots_g   :    integer := 0;
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    keep_slot_g      :    integer := 1;
73
    n_extra_params_g :    integer := 0;
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    cfg_we_g         :    integer := 0;
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    cfg_re_g         :    integer := 0;
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    debug_width_g    :    integer := 0
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    );
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  port (
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    clk              : in std_logic;
80
    rst_n            : in std_logic;
81
 
82
    -- from bus
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    lock_in : in std_logic;
84
    full_in : in std_logic;
85
 
86
    -- from rx
87
    cfg_data_in     : in std_logic_vector (data_width_g -1 downto 0);
88
    cfg_addr_in     : in std_logic_vector (cfg_addr_width_g -1 downto 0);
89
    cfg_ret_addr_in : in std_logic_vector (addr_width_g -1 downto 0);
90
    cfg_re_in       : in std_logic;
91
    cfg_we_in       : in std_logic;
92
 
93
    -- from fifo
94
    av_in    : in std_logic;
95
    data_in  : in std_logic_vector (data_width_g-1 downto 0);
96
    comm_in  : in std_logic_vector (comm_width_g-1 downto 0);
97
    empty_in : in std_logic;
98
    one_d_in : in std_logic;
99
 
100
    -- to bus
101
    av_out   : out std_logic;
102
    data_out : out std_logic_vector (data_width_g-1 downto 0);
103
    comm_out : out std_logic_vector (comm_width_g-1 downto 0);
104
    lock_out : out std_logic;
105
 
106
    -- to rx
107
    cfg_rd_rdy_out : out std_logic;
108
 
109
    -- to fifo
110
    re_out : out std_logic
111
 
112
    -- synthesis translate_off 
113
    ;                                   -- loppusulku ed. portille (wow!)
114
 
115
    debug_out : out std_logic_vector(debug_width_g-1 downto 0);
116
    debug_in : in std_logic_vector(debug_width_g-1 downto 0)
117
    -- synthesis translate_on      
118
 
119
    );
120
end transmitter;
121
 
122
 
123
-- **********
124
-- 19.08.2004
125
-- These must be connected from cfg_mem to tx_ctrl!
126
--  signal Power_Mode_cm_tx        : std_logic_vector ( 1 downto 0);
127
--  signal Competition_Type_cm_tx  : std_logic_vector ( 1 downto 0); 
128
-- **********
129
 
130
 
131
 
132
 
133
architecture structural of transmitter is
134
 
135
 
136
  signal curr_slot_ends_cm_tx   : std_logic;
137
  signal curr_slot_own_cm_tx    : std_logic;
138
  signal next_slot_starts_cm_tx : std_logic;
139
  signal next_slot_own_cm_tx    : std_logic;
140
 
141
  signal n_agents_cm_tx : std_logic_vector (id_width_g-1 downto 0);
142
  signal max_send_cm_tx : std_logic_vector (counter_width_g-1 downto 0);
143
  signal prior_cm_tx    : std_logic_vector (id_width_g-1 downto 0);
144
  signal data_cm_tx     : std_logic_vector (data_width_g-1 downto 0);
145
 
146
  -- These must be connected to tx_ctrl!
147
  signal pwr_mode_cm_tx : std_logic_vector (1 downto 0);
148
  signal arb_type_cm_tx : std_logic_vector (1 downto 0);
149
 
150
 
151
  component tx_control
152
    generic (
153
      counter_width_g : integer := 8;
154
      id_width_g      : integer := 4;
155
      id_g            : integer := 1;   -- not neede?
156
      data_width_g    : integer := 32;  -- in bits
157
      addr_width_g    : integer := 32;  -- in BITS!
158
      comm_width_g    : integer := 3;
159
      n_agents_g      : integer := 0;      -- 2009-04-08
160
      cfg_re_g        : integer := 0;
161
      keep_slot_g     : integer := 1
162
      );
163
    port (
164
      clk                 : in  std_logic;
165
      rst_n               : in  std_logic;
166
      lock_in             : in  std_logic;
167
      full_in             : in  std_logic;  --nyk. data/osoite ei mennyt perille!
168
      cfg_ret_addr_in     : in  std_logic_vector (addr_width_g-1 downto 0);
169
      cfg_data_in         : in  std_logic_vector (data_width_g-1 downto 0);
170
      cfg_re_in           : in  std_logic;
171
      curr_slot_own_in    : in  std_logic;
172
      curr_slot_ends_in   : in  std_logic;
173
      next_slot_own_in    : in  std_logic;
174
      next_slot_starts_in : in  std_logic;
175
      max_send_in         : in  std_logic_vector (counter_width_g-1 downto 0);
176
      n_agents_in         : in  std_logic_vector (id_width_g-1 downto 0);
177
      prior_in            : in  std_logic_vector (id_width_g-1 downto 0);
178
      -- *********************************************************
179
      -- new ports: Power_Mode and Competition_Type must be added!
180
      -- *********************************************************
181
      arb_type_in         : in  std_logic_vector(1 downto 0);
182
      av_in               : in  std_logic;
183
      data_in             : in  std_logic_vector (data_width_g-1 downto 0);
184
      comm_in             : in  std_logic_vector (comm_width_g-1 downto 0);
185
      one_d_in            : in  std_logic;
186
      empty_in            : in  std_logic;
187
      av_out              : out std_logic;
188
      data_out            : out std_logic_vector (data_width_g-1 downto 0);
189
      comm_out            : out std_logic_vector (comm_width_g-1 downto 0);
190
      lock_out            : out std_logic;
191
      cfg_rd_rdy_out      : out std_logic;
192
      re_out              : out std_logic
193
      );
194
  end component;  --tx_control;
195
 
196
  component cfg_mem
197
    generic (
198
      id_width_g       : integer := 4;
199
      id_g             : integer := 5;
200
      base_id_g        : integer := 5;
201
      data_width_g     : integer := 16;  -- in bits
202
--      addr_width_g         :     integer := 16;           -- in bits,
203
--      19.12.2005 ak
204
      counter_width_g  : integer := 8;
205
      arb_type_g       : integer := 0;
206
      cfg_addr_width_g : integer := 7;   -- 16.12.05
207
      -- page_addr_width_g    :     integer := 2;  -- change to constant
208
      -- param_addr_width_g   :     integer := 5;  -- change to constant
209
      inv_addr_en_g    : integer := 0;   -- not used?
210
      addr_g           : integer := 46;
211
      prior_g          : integer := 2;
212
      max_send_g       : integer := 50;
213
      n_agents_g       : integer := 4;
214
      n_cfg_pages_g    : integer := 1;
215
      n_time_slots_g   : integer := 0;
216
--      n_extra_params_g     :     integer := 0;--19.12.05 AK
217
      cfg_re_g         : integer := 0;   -- 28.02.005
218
      cfg_we_g         : integer := 0    -- 28.02.005
219
      --cfg_rom_en_g   : integer := 0   -- 28.02.005
220
      );
221
    port (
222
      clk   : in std_logic;
223
      rst_n : in std_logic;
224
 
225
      -- addr_in could be narrower, since id is only in addr decoder
226
      addr_in              : in  std_logic_vector (cfg_addr_width_g -1 downto 0);  --04.03.05
227
      -- addr_in              : in  std_logic_vector ( page_addr_width_g + param_addr_width_g -1 downto 0);  --04.03.05
228
      --addr_in              : in  std_logic_vector ( addr_width_g -1 downto 0);
229
      data_in              : in  std_logic_vector (data_width_g-1 downto 0);
230
      re_in                : in  std_logic;
231
      we_in                : in  std_logic;
232
      curr_slot_ends_out   : out std_logic;
233
      curr_slot_own_out    : out std_logic;
234
      next_slot_starts_out : out std_logic;
235
      next_slot_own_out    : out std_logic;
236
      dbg_out              : out integer range 0 to 100;  -- For debug
237
      data_out             : out std_logic_vector (data_width_g-1 downto 0);
238
      arb_type_out         : out std_logic_vector (1 downto 0);
239
      n_agents_out         : out std_logic_vector (id_width_g-1 downto 0);
240
      max_send_out         : out std_logic_vector (counter_width_g-1 downto 0);
241
      prior_out            : out std_logic_vector (id_width_g-1 downto 0);
242
      pwr_mode_out         : out std_logic_vector (1 downto 0)
243
      );
244
  end component;  --cfg_mem;
245
 
246
 
247
 
248
begin  -- structural
249
 
250
  -- Design compiler ei ymmärrä alempaa esittelyä
251
  tx_c : tx_control
252
    -- tx_c : entity work.tx_control
253
    generic map(
254
      counter_width_g => counter_width_g,  --19.05
255
      id_g            => id_g,
256
      id_width_g      => id_width_g,
257
      data_width_g    => data_width_g,
258
      addr_width_g    => addr_width_g,
259
      comm_width_g    => comm_width_g,
260
      n_agents_g      => n_agents_g,       -- 2009-04-08
261
      cfg_re_g        => cfg_re_g,
262
      keep_slot_g     => keep_slot_g
263
      )
264
    port map(
265
      clk   => clk,
266
      rst_n => rst_n,
267
 
268
      lock_in         => lock_in,
269
      full_in         => full_in,
270
      cfg_data_in     => data_cm_tx,
271
      cfg_ret_addr_in => cfg_ret_addr_in,
272
      cfg_re_in       => cfg_re_in,
273
 
274
      curr_slot_own_in    => curr_slot_own_cm_tx,
275
      curr_slot_ends_in   => curr_slot_ends_cm_tx,
276
      next_slot_own_in    => next_slot_own_cm_tx,
277
      next_slot_starts_in => next_slot_starts_cm_tx,
278
      max_send_in         => max_send_cm_tx,
279
      prior_in            => prior_cm_tx,
280
      n_agents_in         => n_agents_cm_tx,
281
      arb_type_in         => arb_type_cm_tx,
282
 
283
      av_in    => av_in,
284
      data_in  => data_in,
285
      comm_in  => comm_in,
286
      empty_in => empty_in,
287
      one_d_in => one_d_in,
288
 
289
      data_out       => data_out,
290
      comm_out       => comm_out,
291
      av_out         => av_out,
292
      lock_out       => lock_out,
293
      cfg_rd_rdy_out => cfg_rd_rdy_out,
294
 
295
      re_out => re_out
296
      );
297
 
298
 
299
  -- Design compiler ei ymmärrä alempaa esittelyä
300
  cm : cfg_mem
301
    --cm : entity work.cfg_mem
302
    generic map(
303
      counter_width_g => counter_width_g,
304
      id_g            => id_g,
305
      id_width_g      => id_width_g,
306
      base_id_g       => base_id_g,
307
 
308
      data_width_g => data_width_g,
309
--      addr_width_g       => addr_width_g,--19.12.05 AK
310
 
311
 
312
      cfg_addr_width_g => cfg_addr_width_g,  --16.12.05
313
      -- page_addr_width_g  => page_addr_width_g,
314
      -- param_addr_width_g => param_addr_width_g,
315
 
316
      addr_g        => addr_g,
317
      prior_g       => prior_g,
318
      inv_addr_en_g => inv_addr_en_g,
319
      max_send_g    => max_send_g,
320
      arb_type_g => arb_type_g,
321
 
322
      n_agents_g     => n_agents_g,
323
      n_cfg_pages_g  => n_cfg_pages_g,
324
      n_time_slots_g => n_time_slots_g,
325
--      n_extra_params_g   => n_extra_params_g,--19.12.05 AK
326
      cfg_re_g       => cfg_re_g,
327
      cfg_we_g       => cfg_we_g
328
      -- cfg_rom_en_g       => cfg_rom_en_g
329
      )
330
    port map(
331
      clk   => clk,
332
      rst_n => rst_n,
333
 
334
      re_in    => cfg_re_in,
335
      we_in    => cfg_we_in,
336
      data_in  => cfg_data_in,
337
      addr_in  => cfg_addr_in,
338
      data_out => data_cm_tx,
339
 
340
      curr_slot_ends_out   => curr_slot_ends_cm_tx,
341
      curr_slot_own_out    => curr_slot_own_cm_tx,
342
      next_slot_starts_out => next_slot_starts_cm_tx,
343
      next_slot_own_out    => next_slot_own_cm_tx,
344
 
345
      arb_type_out => arb_type_cm_tx,
346
      n_agents_out => n_agents_cm_tx,
347
      max_send_out => max_send_cm_tx,
348
      prior_out    => prior_cm_tx,
349
      pwr_mode_out => pwr_mode_cm_tx
350
 
351
      );
352
 
353
 
354
end structural;

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