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-------------------------------------------------------------------------------

-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems

--

-- This source file may be used and distributed without

-- restriction provided that this copyright statement is not

-- removed from the file and that any derivative work contains

-- the original copyright notice and the associated disclaimer.

--

-- This source file is free software; you can redistribute it

-- and/or modify it under the terms of the GNU Lesser General

-- Public License as published by the Free Software Foundation;

-- either version 2.1 of the License, or (at your option) any

-- later version.

--

-- This source is distributed in the hope that it will be

-- useful, but WITHOUT ANY WARRANTY; without even the implied

-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

-- PURPOSE.  See the GNU Lesser General Public License for more

-- details.

--

-- You should have received a copy of the GNU Lesser General

-- Public License along with this source; if not, download it

-- from http://www.opencores.org/lgpl.shtml

-------------------------------------------------------------------------------

-------------------------------------------------------------------------------

-- File        : tx_control_addr_width_is_1_muxed_fifos.vhdl

-- Description : Control the transmitting of data. Includes

--               the priority arbitration. Config mem gives

--               the start and end times and owners  of time slots.

--

--               This version assumes, muxed fifos, i.e. FSM does no

--               separation between messages and data, it sees only one fifo.

-- Author      : Erno Salminen

-- e-mail      : erno.salminen@tut.fi

-- Project      huuhaa

-- Design      : Do not use term design when you mean system

-- Date        : 11.02.2003

-- Modified    :

--

-- 07.01.03     ES:  Next state of Re_tx_data is always idle!

--              This way there are less problems with reading the fifo

-- 17.03.03     ES: Idle->Write won't work if new addr is coming. Cannot assert

--              fifo read enable in time. consequently, tha same is written

--              twice on the bus

-- 12.04.03     ES: Total_amount, Addr_Amount input ports and Fifo_Depth generic removed

-- 13.04.03     ES: Message stuff removed

--              Constant print_debug added, selects wheteher assertions are

--              used or not

-- 04.03.04     ES: two bugs with target_fifo_full

--              1) target_fifo_full=1 when next addr coming from fifo

--                      => addr stored in data_reg2 and sent as if it was data

--                      => add extra reg for that addr and valid_reg for it

--                      => values stored in them state 'write'

--                      => values read from them when retransfer completes

--                      

--              2) next addr comes from fifo before retransfer is complete

--                      => retransfer goes to 'next addr'

--                      => add one confition to if clause in state idle

--                      (inside else clause 'not own turn')

-- 28.07.2004   ES: cleaning, addr_reg type changed to regular std_logic_vector

-- 03.08.2004   ES: Renamed some states to shorter names. New if-branch inside cfg_d

--                  Added debug_level and Rst_Value for wave form debugging.

--                  Set dbg_level=0 for synthesis.    

-- 13.09.2004   ES: Bug found. When target_fifo_full=1 and addr on the bus, the

--                  addr will be retransferred as addr (ok) and as data also (not

--                  ok). Check addr_valid on state write and assign data_r1 and

--                  data_r2 accordingly

--

-- 15.12.2004   ES names changed

--

-- 03.01.2005   ES retx_addr: check fo full=1 added

-- 14.01.2005      when idle and going to own_slot_reservation, check re

-- 15.01.2005   ES idle->own slot res: lock_out must be 1-

-- 03.02.05     ES  addr_width_g is now in BITS!

-- 07.02.05     ES new generic cfg_re_g

-- 15.05.05     AK A bug when writing every other clock cycle, the data after

--                 the address vanishes. suspicious state: idle 2d. and write_data 4).

--                 corrected, hopefully.

--

-- 13.07.05     AK A bug which reads out an address but doesn't send it when

--                 retransmitting. suspicious state: 1 (under 0a). more

--                 explanation there.

-- ?????????

-- 25.02.2005 Design compiler ei välttämättä syntesoi a_ext-funktiota oikein?

-- 2007/04/18   AK/ES Arbitration type voidaan asettaa ajonaikana 4:ään eri arvoon

-- 2009/07/31   JN Cleanups + keep_slot_g (lock_out = '1' trough whole time slot)

------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity tx_control is

  generic (

    counter_width_g : integer := 8;

    id_width_g      : integer := 4;

    id_g            : integer := 1;     -- not neede?

    data_width_g    : integer := 32;    -- in bits

    addr_width_g    : integer := 32;    -- in BITS!

    comm_width_g    : integer := 3;

    n_agents_g      : integer := 0;      -- 2009-04-08

    cfg_re_g        : integer := 0;

    keep_slot_g     : integer := 1      -- 2009-07-31

    );

  port (

    clk   : in std_logic;

    rst_n : in std_logic;

    lock_in : in std_logic;

    full_in : in std_logic;  --nyk. data/osoite ei mennyt perille!

    cfg_ret_addr_in : in std_logic_vector (addr_width_g-1 downto 0);

    cfg_data_in     : in std_logic_vector (data_width_g-1 downto 0);

    cfg_re_in       : in std_logic;

    curr_slot_own_in    : in std_logic;

    curr_slot_ends_in   : in std_logic;

    next_slot_own_in    : in std_logic;

    next_slot_starts_in : in std_logic;

    max_send_in         : in std_logic_vector (counter_width_g-1 downto 0);

    n_agents_in         : in std_logic_vector (id_width_g-1 downto 0);

    prior_in            : in std_logic_vector (id_width_g-1 downto 0);

    -- *********************************************************

    -- new ports: Power_Mode and Competition_Type must be added!

    -- *********************************************************

    -- 0 round-robin, 1 priority, 2 combined, 3 dyn_arb (rand)

    arb_type_in         :    std_logic_vector(1 downto 0);

    av_in    : in std_logic;

    data_in  : in std_logic_vector (data_width_g-1 downto 0);

    comm_in  : in std_logic_vector (comm_width_g-1 downto 0);

    one_d_in : in std_logic;

    empty_in : in std_logic;

    av_out         : out std_logic;

    data_out       : out std_logic_vector (data_width_g-1 downto 0);

    comm_out       : out std_logic_vector (comm_width_g-1 downto 0);

    lock_out       : out std_logic;

    cfg_rd_rdy_out : out std_logic;

    re_out         : out std_logic

    );

end tx_control;

architecture rtl of tx_control is

  constant write_command_c : std_logic_vector (2 downto 0) := "010";  -- 03.02.05

  -- Selects if debug prints are used ('1') or not ('0')

  constant dbg_level : integer range 0 to 3 := 0;  -- 0= no debug, use 0 for synthesis

  -- Registers may be reset to 'Z' to 'X' so that reset state is clearly

  -- distinguished from active state. Using dbg_level+rst_Value array, the rst value may

  -- be easily set to '0' for synthesis.

  constant rst_value_arr : std_logic_vector (6 downto 0) := 'X' & 'Z' & 'X' & 'Z' & 'X' & 'Z' & '0';

  -- Combinatorial signals

  -- Own_turn_ends is high when own turn ends, i.e.

  --  * maximum amount of data sent

  --  * own slot ends

  --  * other slot starts

  --  09.01.04: This seems to be in critical path.

  --  If this was register, critical path could be shortened.

  --  On the other hand comparison must be changed to drive register one cycle

  --  earlier than combinatorial signal. 

  signal own_turn_ends  : std_logic;

  signal prior_match    : std_logic;

  signal max_send_limit : std_logic;

  -- Define type and signals for state machine

  type state_vector is (Idle,

                        Own_Slot_Reservation,

                        Cfg_A, Cfg_D, Cfg_D_Last,

                        Retransfer_Addr, Retransfer_data, Retransfer_Data_Last,

                        Write_Data, Write_Last_Data, Error_State);

  signal curr_state_r : state_vector;

  -- Counters and signals denoting start and end of the competition reservation

  -- Counters do not have to be as wide as data! They generate huge delays

  -- and slow down the whole unit if they are unnecessarily wide!

  signal prior_counter_r : std_logic_vector (id_width_g -1 downto 0);

  signal send_counter_r  : std_logic_vector (counter_width_g -1 downto 0);

  -- Register, this way the state of the signal 'read enable' can be read

  signal fifo_re_r : std_logic;

  signal addr1_r   : std_logic_vector (addr_width_g -1 downto 0);  -- 03.02.05

  signal comm_a1_r : std_logic_vector (comm_width_g -1 downto 0);

  -- Registers needed to continue interrupted transfer

  -- When transfer is interrupted, addr and either 1 or 2 data has be trasferred

  -- again.

  -- (Actually, only one data is retransferered, but have another may already

  -- been read from fifo but not transferred. This is data referred as

  -- retransferred because it is handled in the sama way as the actually

  -- retransferred. It is stored in data_reg2 )

  -- When state is write_data

  --  * Regular data goes from fifo to output registers

  --  * At the same, it is copied ro register data_Reg2

  --  * At he same time, previously sent data is copied from data2_r to data1_r

  --  data1_r is retransferred after addr (and after that data2_r if needed)

  signal data1_r       : std_logic_vector (data_width_g -1 downto 0);

  signal data2_r       : std_logic_vector (data_width_g -1 downto 0);

  signal comm_d1_r     : std_logic_vector (comm_width_g -1 downto 0);

  signal comm_d2_r     : std_logic_vector (comm_width_g -1 downto 0);

  signal retx_amount_r : integer range 0 to 2;

  signal addr_valid_r : std_logic;      -- 13.09.04

  -- For storing new addr that comes at the same with full_in=1

  signal addr2_r       : std_logic_vector (addr_width_g -1 downto 0);  -- 03.02.05

  signal comm_a2_r     : std_logic_vector (comm_width_g -1 downto 0);

  signal addr2_valid_r : std_logic;

  -- Signals for configuration read operation

  signal cfg_ret_addr_r      : std_logic_vector (addr_width_g-1 downto 0);  -- 03.02.05

  signal cfg_read_value_r    : std_logic_vector (data_width_g-1 downto 0);

  signal cfg_read_complete_r : std_logic;

  -- Muutetaan vertailun tulos reksiteriksi

  -- =>  lyhyempi kriittinen polku (toivottavasti)

  signal max_send_limit_r : std_logic;

  -- Katsotaan paljonko tulee viivett�t�� menness�

  signal own_turn_ends_r : std_logic;

  -- prior+round-robin countteri

  -- after this amount of clock cycles, change the arb type

  constant switch_arb_c    : integer := 4096;

  signal   switch_arb_r    : integer range 0 to switch_arb_c-1;

  signal   arb_type_r      : std_logic_vector(1 downto 0);

  signal   curr_arb_type_r : std_logic_vector(1 downto 0);

  -- dynamically adaptive arbitration, enable this for "random arb"

  signal   arb_agent_r      : std_logic_vector(id_width_g-1 downto 0);

--  constant dyn_arb_enable_c : integer := 0;

  constant dyn_arb_enable_c : integer := 1;  -- ES 2009-04-01

  signal dyn_arb_prior       : std_logic_vector(id_width_g-1 downto 0);

  signal prior_counter_arb_r : std_logic_vector(id_width_g-1 downto 0);

  component dyn_arb

    generic (

      id_width_g : integer;

      n_agents_g : integer

      );

    port (

      clk           : in  std_logic;

      rst_n         : in  std_logic;

      bus_lock_in   : in  std_logic;

      arb_agent_out : out std_logic_vector(id_width_g-1 downto 0));

  end component;

begin  -- rtl

  -- Continous assignments to outputs

  cfg_rd_rdy_out <= cfg_read_complete_r;

  re_out         <= fifo_re_r;

  av_out         <= addr_valid_r;       --13.09.04

  -- Sendcounterin vertialu on omalla kellojaksollaan

  -- => ei ole en� kriittisell�polulla

  -- Laskurin reset-arvosta riippuu mitk�send_maxit on laillisia

  -- ja l�etet�nk�tarkalleen se m�r�vai pari enemm�, ao. m�r� sis�t�

  -- ekan osoiteen

  -----------------------------------------------------------------------------

  --   Counterin arvot     L�. m�r�    Sallitus max-sendin arvot

  ------------------------------------------------------------------------------

  -- jos counter= 0,1,2  max_s+3 kpl      max_s= 2,3+

  -- jos counter= 1,2,3  max_s+2 kpl      max_s= 2,3+

  -- jos counter= 2,3,4  max_s+1 kpl      max_s= 3,4+

  -- jos counter= 3,4,5  max_s   kpl      max_s= 4,5+

  -- => ei kannata resetoida ainakaan nollaan!

  max_send_limit <= max_send_limit_r;

  check_max_send : process (clk, rst_n)

  begin  -- process check_max_send

    if rst_n = '0' then

      max_send_limit_r <= '0';

      own_turn_ends_r <= '0';

    elsif clk'event and clk = '1' then

      if (max_send_in (counter_width_g-1 downto 0) = send_counter_r

          or max_send_in = conv_std_logic_vector (0, data_width_g)

          or max_send_in = conv_std_logic_vector (1, data_width_g))

      then

        if (curr_slot_own_in = '1'

            or (next_slot_starts_in = '1' and next_slot_own_in = '1')) then

          max_send_limit_r <= '0';

        else

          max_send_limit_r <= '1';

        end if;

      else

        max_send_limit_r <= '0';

      end if;

      own_turn_ends_r <= own_turn_ends;

    end if;

  end process check_max_send;

  -- 2) COMB PROC

  -- Check if priority matches so that competition reservation may start

  Check_Prior : process (prior_in, prior_counter_r)

  begin  -- process Check_Send_Limit

    if prior_counter_r = prior_in (id_width_g-1 downto 0) then  --22.01.03

      prior_match <= '1';

    else

      prior_match <= '0';

    end if;

  end process Check_Prior;

  -- 3) PROC (ASYNC)

  -- Check if bus reservation must be ended

  -- Own turn ends, if

  -- * max amount data already transferred

  -- * or own slot ends

  -- * or some other wrapper's slot starts

  -- When Own_turn_ends=1, wrapper can transfer one value

  Check_Turn : process (max_send_limit,

                        curr_slot_own_in, curr_slot_ends_in,

                        next_slot_own_in, next_slot_starts_in)

  begin  -- process Check_Turn

    if max_send_limit = '1'

      or ((curr_slot_own_in = '1' and curr_slot_ends_in = '1')

          or (next_slot_own_in = '0' and next_slot_starts_in = '1'))then

      own_turn_ends <= '1';

    else

      own_turn_ends <= '0';

    end if;

  end process Check_Turn;

  -- 4) SEQ PROC

  -- Count how many data has been transferred

  -- Counter is not incremented, if

  -- * wrapper is not trasferring

  -- * wrapper has a time slot

  -- * wrapper is finishing transfer

  Count_Sent_Items : process (clk, rst_n)

  begin  -- process Count_Sent_Items

    if rst_n = '0' then                 -- asynchronous reset (active low)

      send_counter_r <= (others => '0');

    elsif clk'event and clk = '1' then  -- rising clock edge

      if curr_state_r = Idle

        or curr_slot_own_in = '1'

        or curr_state_r = Write_Last_Data

        or curr_state_r = Retransfer_Data_Last

        or curr_state_r = Cfg_D_Last then

        send_counter_r <= (others => '0');

        send_counter_r(1) <= '1';       -- 12.12.05 reset to 0x002

        send_counter_r(0) <= '1';       -- 12.12.05 reset to 0x001

        -- Counter should be incremented already when moving from idle to

        -- some write state (Write_Data / Cfg_A / Retransfer_Addr)!

        -- At the moment, counter is started one clock cycle too late

        -- => send_max+1 data will be transferred

        -- 31.07 can this be fixed, if counter was reset to 1

        else

        if curr_slot_own_in = '1'

          or (next_slot_starts_in = '1' and next_slot_own_in = '1') then

          send_counter_r <= (others => '0');

        else

          send_counter_r <= send_counter_r +1;

        end if;  -- curr_slot_own_in

      end if;  -- Curr_State

    end if;  -- rst_n/clk'event

  end process Count_Sent_Items;

  -- 5) SEQ PROC

  Define_output : process (clk, rst_n)

    variable lock_v : std_logic;

  begin  -- process Define_output

    if rst_n = '0' then

      lock_out     <= '0';

      addr_valid_r <= '0';

      comm_out     <= (others => '0');

      data_out     <= (others => '0');

      data1_r       <= (others => rst_value_arr (dbg_level* 1));

      data2_r       <= (others => rst_value_arr (dbg_level* 1));

      comm_d1_r     <= (others => rst_value_arr (dbg_level* 1));

      comm_d2_r     <= (others => rst_value_arr (dbg_level* 1));

      addr1_r       <= (others => rst_value_arr (dbg_level* 1));

      addr2_r       <= (others => rst_value_arr (dbg_level* 1));

      comm_a1_r     <= (others => rst_value_arr (dbg_level* 1));

      comm_a2_r     <= (others => rst_value_arr (dbg_level* 1));

      addr2_valid_r <= '0';

      fifo_re_r           <= '0';

      cfg_read_complete_r <= '1';

      cfg_read_value_r    <= (others => rst_value_arr (dbg_level* 1));

      cfg_ret_addr_r      <= (others => rst_value_arr (dbg_level* 1));

      retx_amount_r <= 0;

      curr_state_r  <= Idle;

    elsif clk'event and clk = '1' then

      -- checks that the command is being fed with data.

      assert (empty_in = '1' or (empty_in = '0' and comm_in /= "000")) report "Comm warning! idle from FIFO" severity error;

      -- default value, just in case..

      lock_v := '0';

      -- Control the configuration registers

      -- Read conf value from conf mem to register

      if cfg_re_g = 1

        and cfg_re_in = '1' then

        cfg_ret_addr_r      <= cfg_ret_addr_in;

        cfg_read_value_r    <= cfg_data_in;

        cfg_read_complete_r <= '0';

      else

        if curr_state_r = Cfg_D_Last

          or curr_state_r = Cfg_D then

          if full_in = '0' then

            -- Answering to conf read succeeded

            cfg_read_complete_r <= '1';

          else

            -- Answering did not succeed

            cfg_read_complete_r <= '0';

            assert dbg_level < 2 report "Conf (Last) D : Ei onnistunut" severity note;

          end if;

        end if;

      end if;

      -- Control other registers

      -- Register values are updated when state changes

      -- (i.e. the assigment clause is in the previous state in the code)

      -- => e.g. addr is written when moving idle->Retransfer_Addr

      -- => when state=Retransfer_Addr :

      --    *  bus=addr and data_out_reg <= next data

      case curr_state_r is

        --++++++++++++++        

        when Idle =>

          -- (0a Something to transmit, own turn not ending

          --  0b Nothing to do)

          -- 1) Own time slot starts

          -- 2) Competition 

          --    2a) Re_transmit

          --    2b) Answer conf read

          --    2c) New addr+data

          --    2d) New addr but no data, stop. Remove this branch?

          --    2e) New data, use old addr

          --    2f) Illegal?

          -- 3) Not own turn

          --

          if own_turn_ends = '0'

            and (empty_in = '0'

                 or (cfg_re_g = 1 and cfg_read_complete_r = '0')

                 or retx_amount_r /= 0) then

            -- 0a)

            if next_slot_own_in = '1' and next_slot_starts_in = '1' then

              -- 1) Own time slot starts

              lock_v       := '1';

              addr_valid_r <= '0';

              addr_valid_r <= '0';

              data_out     <= (others => '0');

              comm_out     <= (others => '0');

              assert false report "????????????????????????????????????????" severity warning;

              assert false report "tx_ctrl/idle: Suspicious if-elsif branch (own slot starts)" severity warning;

              if (fifo_re_r = '0'

                  and retx_amount_r = 0

                  and empty_in = '0' and av_in = '1' and one_d_in = '1') then

                fifo_re_r    <= '1';            -- 02.06.06 es

                addr1_r      <= data_in (addr_width_g -1 downto 0);  -- 02.06.06 es

                comm_a1_r    <= comm_in;        -- 02.06.06 es

                curr_state_r <= idle;           -- 05.06.2006

                assert dbg_level < 1 report "idle : oma aikaslotti alkaa, mutta vain 1 osoite fifossa" severity note;

              elsif (fifo_re_r = '0'

                     and retx_amount_r = 0

                     and empty_in = '0' and av_in = '1' and one_d_in = '0') then

                -- 05.06.06 es

                fifo_re_r    <= '1';

                addr1_r      <= data_in (addr_width_g -1 downto 0);

                comm_a1_r    <= comm_in;

                curr_state_r <= Own_Slot_Reservation;

                assert dbg_level < 1 report "idle : oma aikaslotti alkaa, 05.06.2006 Brand new!" severity note;

              else

                fifo_re_r    <= '0';

                assert dbg_level < 1 report "idle : oma aikaslotti alkaa +re = 0" severity note;

                curr_state_r <= Own_Slot_Reservation;

              end if;

              -- Why did we read out the address? it wasn't even stored anywhere.

              -- It seems that address needs to be read in some cases, but in some

              -- it must not be! The bug can be seen in the tx control testbench.

              -- However, simply setting fifo_re_r <= '0'; doesn't solve the problems;

              -- it causes more.

              -- Bug was discovered with video system, where (erratically) n_time_slots

              -- was one although timeslots are not used.

              -- 13.7.05 AK

              assert false report "????????????????????????????????????????" severity warning;

            elsif (next_slot_starts_in = '0' and prior_match = '1'

              and (lock_in = '0')) or (keep_slot_g = 1 and curr_slot_own_in = '1')

            then

              -- 2) Competition

              -- Note: Order. 1) retx, 2) cfg and so on

              -- Note! 21.01.2003

              -- Comparison (lock_in = '1' and full_in = '1') caused

              -- problems, when receiver asserts full=1 during addr phase.

              -- (Receiver _should_ assert target_full only during data phase but

              -- you never know)

              -- Then trasmitter puts data on the bus but the next wrapper may

              -- put its own addr on the at same time => conflict

              assert dbg_level < 3 report "Kilpailuvuoro" severity note;

              if retx_amount_r /= 0 then

                -- 2a) Receiver got full last time

                curr_state_r                       <= Retransfer_Addr;

                addr_valid_r                       <= '1';

                data_out                           <= (others => '0');  -- 01.03.05

                data_out (addr_width_g-1 downto 0) <= addr1_r;  -- 01.03.05

                comm_out                           <= comm_a1_r;

                lock_v                             := '1';

                fifo_re_r                          <= '0';

                assert dbg_level < 3 report "Idle : uusiolahetys" severity note;

                -- 25.01.05 elsif cfg_read_complete_r = '0' then

              elsif cfg_re_g = 1 and cfg_read_complete_r = '0' then

                -- 2b) Conf read has not been yet answered

                -- Answered conf values don't have to be stored in addr_reg/data_reg

                curr_state_r                       <= Cfg_A;

                addr_valid_r                       <= '1';

                data_out                           <= (others => '0');  -- 01.03.05

                data_out (addr_width_g-1 downto 0) <= cfg_ret_addr_r;  -- 01.03.05

                comm_out                           <= write_command_c;  -- 03.02.05

                lock_v                             := '1';

                fifo_re_r                          <= '0';

                assert dbg_level < 3 report "idle : vastataan konf. lukuun" severity note;

--              elsif (empty_in = '0' and av_in = '1' and one_d_in = '0') then

                -- 2c) New addr and data

--                assert dbg_level < 3 report "idle : uusi osoite" severity note;

                -- Take the safe way, stay in idle until addr is read from the

                -- fifo 17.03.03

--                curr_state_r <= Idle;

--                addr_valid_r <= '0';

--                data_out     <= (others => '0');

--                comm_out     <= (others => '0');

--                lock_v       := '0';

--                fifo_re_r    <= '0';

                -- AK 12.05.05

              elsif (empty_in = '0' and av_in = '1') then -- and one_d_in = '1') then

                -- 2d) Only new addr but no data

                curr_state_r <= Idle;

                addr_valid_r <= '0';

                comm_out     <= (others => '0');

                data_out     <= (others => '0');

                lock_v       := '0';

                -- 13.05.2005 ES

                if fifo_re_r = '0' then

                  addr1_r   <= data_in (addr_width_g -1 downto 0);  -- 03.02.05

                  comm_a1_r <= comm_in;

                  fifo_re_r <= '1';

                else

                  fifo_re_r <= '0';

                end if;

                assert dbg_level < 3 report "idle : pelkastaan uusi osoite (ei laheteta)" severity note;

              elsif (empty_in = '0' and av_in = '0') then

                -- 2e) Data coming from fifo

                -- Transfer previous addr again

                curr_state_r                       <= Retransfer_Addr;

                addr_valid_r                       <= '1';

                data_out                           <= (others => '0');  -- 01.03.05

                data_out (addr_width_g-1 downto 0) <= addr1_r;  -- 01.03.05

                comm_out                           <= comm_a1_r;

                lock_v                             := '1';

                fifo_re_r                          <= '1';

                assert dbg_level < 3 report "idle : ed data jatkuu" severity note;

              else

                -- 2f) Illegal (?) branch

                curr_state_r <= Error_State;

                -- 22.07 Actually this branch may be reached if fifo has one addr

                -- but no data

                addr_valid_r <= '0';

                data_out     <= (others => '0');

                comm_out     <= (others => '0');

                lock_v       := '0';

                assert false report "Idle => Error_state" severity error;

                assert av_in = '1' report "AV on 0" severity note;

                assert av_in = '0' report "AV on 1" severity note;

                assert empty_in = '1' report "empty_in on 0" severity note;

                assert empty_in = '0' report "empty_in on 1" severity note;

                assert one_d_in = '1' report "one_d_in on 0" severity note;

                assert one_d_in = '0' report "one_d_in on 1" severity note;

              end if;  -- re_tx_amount

            else

              -- 3) Not own turn

              curr_state_r <= Idle;

              addr_valid_r <= '0';

              data_out     <= (others => '0');

              comm_out     <= (others => '0');

              lock_v       := '0';

              assert dbg_level < 3 report "Idle : Odotetaan omaa vuoroa" severity note;