URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [ip_xact/] [hibi_orbus_6p.3.0.xml] - Blame information for rev 158

Go to most recent revision | Details | Compare with Previous | View Log








        TUT
        ip.hwp.communication
        hibi_orbus_6p
        3.0
        
                
                        master
                        HIBI bus <---> wrapper master interface
                        
                        
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_av_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                bus_comm_out
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                bus_data_out
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_full_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOCK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_lock_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        slave_0
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_av_0_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                bus_comm_0_in
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                bus_data_0_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_full_0_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOCK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_lock_0_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        slave_1
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_av_1_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                bus_comm_1_in
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                bus_data_1_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_full_1_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOCK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_lock_1_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        slave_2
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_av_2_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                bus_comm_2_in
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                bus_data_2_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_full_2_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOCK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_lock_2_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        slave_3
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                                
                        
                        false
                        
                                
                                        
                                                AV
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_av_3_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                COMM
                                                
                                                        4
                                                        0
                                                
                                        
                                        
                                                bus_comm_3_in
                                                
                                                        4
                                                        0
                                                
                                        
                                
                                
                                        
                                                DATA
                                                
                                                        31
                                                        0
                                                
                                        
                                        
                                                bus_data_3_in
                                                
                                                        31
                                                        0
                                                
                                        
                                
                                
                                        
                                                FULL
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_full_3_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                LOCK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                bus_lock_3_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        slave_4
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                        false
                        8
                        little
                
                
                        slave_5
                        HIBI bus <---> wrapper slave interface
                        
                        
                        
                        false
                        8
                        little
                
        
        
                
                        
                                rtl
                                ::
                                hibi_orbus_6p
                                
                                        hdlSources
                                
                        
                
                
                        
                                bus_av_0_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_av_1_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_av_2_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_av_3_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_av_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                bus_comm_0_in
                                
                                        in
                                        
                                                4
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_comm_1_in
                                
                                        in
                                        
                                                4
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_comm_2_in
                                
                                        in
                                        
                                                4
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_comm_3_in
                                
                                        in
                                        
                                                4
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_comm_out
                                
                                        out
                                        
                                                4
                                                0
                                        
                                
                                
                        
                        
                                bus_data_0_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_data_1_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_data_2_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_data_3_in
                                
                                        in
                                        
                                                31
                                                0
                                        
                                        
                                                (others => '0')
                                        
                                
                                
                        
                        
                                bus_data_out
                                
                                        out
                                        
                                                31
                                                0
                                        
                                
                                
                        
                        
                                bus_full_0_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_full_1_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_full_2_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_full_3_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_full_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                        
                                bus_lock_0_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_lock_1_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_lock_2_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_lock_3_in
                                
                                        in
                                        
                                                '0'
                                        
                                
                                
                        
                        
                                bus_lock_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                
                                
                        
                
                
                        
                                comm_width_g
                                HIBI command width
                                5
                        
                        
                                data_width_g
                                HIBI data width
                                32
                        
                
        
        
                
                        hdlSources
                        VHDL for HIBI orbus to connect four hibi wrappers
                        
                                ../vhd/hibi_orbus_6p.vhd
                                vhdlSource
                                false
                        
                        
                                vhdlSource
                                vcom
                                 -work hibi -check_synthesis -quiet 
                                false
                        
                
        
        
                
                        
                                IP
                                HW
                                Parameterizable
                        
                
        


Browse

Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [ip_xact/] [hibi_orbus_6p.3.0.xml] - Blame information for rev 158

Line No.	Rev	Author	Line
1	155	lanttu
2
3
4
5
6
7			`TUT`
8			`ip.hwp.communication`
9			`hibi_orbus_6p`
10			`3.0`
11
12
13			`master`
14			`HIBI bus <---> wrapper master interface`
15
16
17
18			`false`
19
20
21
22			`AV`
23
24			`0`
25			`0`
26
27
28
29			`bus_av_out`
30
31			`0`
32			`0`
33
34
35
36
37
38			`COMM`
39
40			`4`
41			`0`
42
43
44
45			`bus_comm_out`
46
47			`4`
48			`0`
49
50
51
52
53
54			`DATA`
55
56			`31`
57			`0`
58
59
60
61			`bus_data_out`
62
63			`31`
64			`0`
65
66
67
68
69
70			`FULL`
71
72			`0`
73			`0`
74
75
76
77			`bus_full_out`
78
79			`0`
80			`0`
81
82
83
84
85
86			`LOCK`
87
88			`0`
89			`0`
90
91
92
93			`bus_lock_out`
94
95			`0`
96			`0`
97
98
99
100
101			`8`
102			`little`
103
104
105			`slave_0`
106			`HIBI bus <---> wrapper slave interface`
107
108
109
110
111
112			`false`
113
114
115
116			`AV`
117
118			`0`
119			`0`
120
121
122
123			`bus_av_0_in`
124
125			`0`
126			`0`
127
128
129
130
131
132			`COMM`
133
134			`4`
135			`0`
136
137
138
139			`bus_comm_0_in`
140
141			`4`
142			`0`
143
144
145
146
147
148			`DATA`
149
150			`31`
151			`0`
152
153
154
155			`bus_data_0_in`
156
157			`31`
158			`0`
159
160
161
162
163
164			`FULL`
165
166			`0`
167			`0`
168
169
170
171			`bus_full_0_in`
172
173			`0`
174			`0`
175
176
177
178
179
180			`LOCK`
181
182			`0`
183			`0`
184
185
186
187			`bus_lock_0_in`
188
189			`0`
190			`0`
191
192
193
194
195			`8`
196			`little`
197
198
199			`slave_1`
200			`HIBI bus <---> wrapper slave interface`
201
202
203
204
205
206			`false`
207
208
209
210			`AV`
211
212			`0`
213			`0`
214
215
216
217			`bus_av_1_in`
218
219			`0`
220			`0`
221
222
223
224
225
226			`COMM`
227
228			`4`
229			`0`
230
231
232
233			`bus_comm_1_in`
234
235			`4`
236			`0`
237
238
239
240
241
242			`DATA`
243
244			`31`
245			`0`
246
247
248
249			`bus_data_1_in`
250
251			`31`
252			`0`
253
254
255
256
257
258			`FULL`
259
260			`0`
261			`0`
262
263
264
265			`bus_full_1_in`
266
267			`0`
268			`0`
269
270
271
272
273
274			`LOCK`
275
276			`0`
277			`0`
278
279
280
281			`bus_lock_1_in`
282
283			`0`
284			`0`
285
286
287
288
289			`8`
290			`little`
291
292
293			`slave_2`
294			`HIBI bus <---> wrapper slave interface`
295
296
297
298
299
300			`false`
301
302
303
304			`AV`
305
306			`0`
307			`0`
308
309
310
311			`bus_av_2_in`
312
313			`0`
314			`0`
315
316
317
318
319
320			`COMM`
321
322			`4`
323			`0`
324
325
326
327			`bus_comm_2_in`
328
329			`4`
330			`0`
331
332
333
334
335
336			`DATA`
337
338			`31`
339			`0`
340
341
342
343			`bus_data_2_in`
344
345			`31`
346			`0`
347
348
349
350
351
352			`FULL`
353
354			`0`
355			`0`
356
357
358
359			`bus_full_2_in`
360
361			`0`
362			`0`
363
364
365
366
367
368			`LOCK`
369
370			`0`
371			`0`
372
373
374
375			`bus_lock_2_in`
376
377			`0`
378			`0`
379
380
381
382
383			`8`
384			`little`
385
386
387			`slave_3`
388			`HIBI bus <---> wrapper slave interface`
389
390
391
392
393
394			`false`
395
396
397
398			`AV`
399
400			`0`
401			`0`
402
403
404
405			`bus_av_3_in`
406
407			`0`
408			`0`
409
410
411
412
413
414			`COMM`
415
416			`4`
417			`0`
418
419
420
421			`bus_comm_3_in`
422
423			`4`
424			`0`
425
426
427
428
429
430			`DATA`
431
432			`31`
433			`0`
434
435
436
437			`bus_data_3_in`
438
439			`31`
440			`0`
441
442
443
444
445
446			`FULL`
447
448			`0`
449			`0`
450
451
452
453			`bus_full_3_in`
454
455			`0`
456			`0`
457
458
459
460
461
462			`LOCK`
463
464			`0`
465			`0`
466
467
468
469			`bus_lock_3_in`
470
471			`0`
472			`0`
473
474
475
476
477			`8`
478			`little`
479
480
481			`slave_4`
482			`HIBI bus <---> wrapper slave interface`
483
484
485
486			`false`
487			`8`
488			`little`
489
490
491			`slave_5`
492			`HIBI bus <---> wrapper slave interface`
493
494
495
496			`false`
497			`8`
498			`little`
499
500
501
502
503
504			`rtl`
505			`::`
506	158	lanttu	`hibi_orbus_6p`
507	155	lanttu
508			`hdlSources`
509
510
511
512
513
514			`bus_av_0_in`
515
516			`in`
517
518			`0`
519			`0`
520
521
522			`'0'`
523
524
525
526
527
528			`bus_av_1_in`
529
530			`in`
531
532			`0`
533			`0`
534
535
536			`'0'`
537
538
539
540
541
542			`bus_av_2_in`
543
544			`in`
545
546			`'0'`
547
548
549
550
551
552			`bus_av_3_in`
553
554			`in`
555
556			`'0'`
557
558
559
560
561
562			`bus_av_out`
563
564			`out`
565
566			`0`
567			`0`
568
569
570
571
572
573			`bus_comm_0_in`
574
575			`in`
576
577			`4`
578			`0`
579
580
581			`(others => '0')`
582
583
584
585
586
587			`bus_comm_1_in`
588
589			`in`
590
591			`4`
592			`0`
593
594
595			`(others => '0')`
596
597
598
599
600
601			`bus_comm_2_in`
602
603			`in`
604
605			`4`
606			`0`
607
608
609			`(others => '0')`
610
611
612
613
614
615			`bus_comm_3_in`
616
617			`in`
618
619			`4`
620			`0`
621
622
623			`(others => '0')`
624
625
626
627
628
629			`bus_comm_out`
630
631			`out`
632
633			`4`
634			`0`
635
636
637
638
639
640			`bus_data_0_in`
641
642			`in`
643
644			`31`
645			`0`
646
647
648			`(others => '0')`
649
650
651
652
653
654			`bus_data_1_in`
655
656			`in`
657
658			`31`
659			`0`
660
661
662			`(others => '0')`
663
664
665
666
667
668			`bus_data_2_in`
669
670			`in`
671
672			`31`
673			`0`
674
675
676			`(others => '0')`
677
678
679
680
681
682			`bus_data_3_in`
683
684			`in`
685
686			`31`
687			`0`
688
689
690			`(others => '0')`
691
692
693
694
695
696			`bus_data_out`
697
698			`out`
699
700			`31`
701			`0`
702
703
704
705
706
707			`bus_full_0_in`
708
709			`in`
710
711			`0`
712			`0`
713
714
715			`'0'`
716
717
718
719
720
721			`bus_full_1_in`
722
723			`in`
724
725			`'0'`
726
727
728
729
730
731			`bus_full_2_in`
732
733			`in`
734
735			`'0'`
736
737
738
739
740
741			`bus_full_3_in`
742
743			`in`
744
745			`'0'`
746
747
748
749
750
751			`bus_full_out`
752
753			`out`
754
755			`0`
756			`0`
757
758
759
760
761
762			`bus_lock_0_in`
763
764			`in`
765
766			`0`
767			`0`
768
769
770			`'0'`
771
772
773
774
775
776			`bus_lock_1_in`
777
778			`in`
779
780			`'0'`
781
782
783
784
785
786			`bus_lock_2_in`
787
788			`in`
789
790			`'0'`
791
792
793
794
795
796			`bus_lock_3_in`
797
798			`in`
799
800			`'0'`
801
802
803
804
805
806			`bus_lock_out`
807
808			`out`
809
810			`0`
811			`0`
812
813
814
815
816
817
818
819			`comm_width_g`
820			`HIBI command width`
821			`5`
822
823
824			`data_width_g`
825			`HIBI data width`
826			`32`
827
828
829
830
831
832			`hdlSources`
833			`VHDL for HIBI orbus to connect four hibi wrappers`
834
835	158	lanttu	`../vhd/hibi_orbus_6p.vhd`
836	155	lanttu	`vhdlSource`
837			`false`
838
839
840			`vhdlSource`
841			`vcom`
842			`-work hibi -check_synthesis -quiet`
843			`false`
844
845
846
847
848
849
850			`IP`
851			`HW`
852			`Parameterizable`
853
854
855
856