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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [ip_xact/] [hibi_wrapper_r4.3.0.xml] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu
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3
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        TUT
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        ip.hwp.communication
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        hibi_wrapper_r4
10 
        3.0
11 
        HIBI bus wrapper, interface revision 4
12
13
14 
                        bus_mMaster
15 
                        HIBI bus interface
16
17
18
19 
                        false
20
21
22
23 
                                                FULL
24
25 
                                                        0
26 
                                                        0
27
28
29
30 
                                                bus_full_in
31
32 
                                                        0
33 
                                                        0
34
35
36
37
38
39 
                                                LOCK
40
41 
                                                        0
42 
                                                        0
43
44
45
46 
                                                bus_lock_in
47
48 
                                                        0
49 
                                                        0
50
51
52
53
54
55 
                                                DATA
56
57 
                                                        31
58 
                                                        0
59
60
61
62 
                                                bus_data_in
63
64 
                                                        31
65 
                                                        0
66
67
68
69
70
71 
                                                COMM
72
73 
                                                        4
74 
                                                        0
75
76
77
78 
                                                bus_comm_in
79
80 
                                                        4
81 
                                                        0
82
83
84
85
86
87 
                                                AV
88
89 
                                                        0
90 
                                                        0
91
92
93
94 
                                                bus_av_in
95
96 
                                                        0
97 
                                                        0
98
99
100
101
102 
                        8
103 
                        little
104
105
106 
                        bus_mSlave
107
108
109
110 
                        false
111
112
113
114 
                                                LOCK
115
116 
                                                        0
117 
                                                        0
118
119
120
121 
                                                bus_lock_out
122
123 
                                                        0
124 
                                                        0
125
126
127
128
129
130 
                                                FULL
131
132 
                                                        0
133 
                                                        0
134
135
136
137 
                                                bus_full_out
138
139 
                                                        0
140 
                                                        0
141
142
143
144
145
146 
                                                DATA
147
148 
                                                        31
149 
                                                        0
150
151
152
153 
                                                bus_data_out
154
155 
                                                        31
156 
                                                        0
157
158
159
160
161
162 
                                                AV
163
164 
                                                        0
165 
                                                        0
166
167
168
169 
                                                bus_av_out
170
171 
                                                        0
172 
                                                        0
173
174
175
176
177
178 
                                                COMM
179
180 
                                                        4
181 
                                                        0
182
183
184
185 
                                                bus_comm_out
186
187 
                                                        4
188 
                                                        0
189
190
191
192
193 
                        8
194 
                        little
195
196
197 
                        ip_mMaster
198 
                        HIBI IP  mirrored master interface revision 4.
199
200
201
202 
                        false
203
204
205
206 
                                                AV
207
208 
                                                        0
209 
                                                        0
210
211
212
213 
                                                agent_av_in
214
215 
                                                        0
216 
                                                        0
217
218
219
220
221
222 
                                                COMM
223
224 
                                                        4
225 
                                                        0
226
227
228
229 
                                                agent_comm_in
230
231 
                                                        4
232 
                                                        0
233
234
235
236
237
238 
                                                DATA
239
240 
                                                        31
241 
                                                        0
242
243
244
245 
                                                agent_data_in
246
247 
                                                        31
248 
                                                        0
249
250
251
252
253
254 
                                                RE
255
256 
                                                        0
257 
                                                        0
258
259
260
261 
                                                agent_re_in
262
263 
                                                        0
264 
                                                        0
265
266
267
268
269
270 
                                                WE
271
272 
                                                        0
273 
                                                        0
274
275
276
277 
                                                agent_we_in
278
279 
                                                        0
280 
                                                        0
281
282
283
284
285 
                        8
286 
                        little
287
288
289 
                        ip_mSlave
290 
                        HIBI IP  mirrored slave interface revision 4.
291
292
293
294
295 
                                        addr_g
296 
                                        addr_limit_g
297
298
299 
                        false
300
301
302
303 
                                                AV
304
305 
                                                        0
306 
                                                        0
307
308
309
310 
                                                agent_av_out
311
312 
                                                        0
313 
                                                        0
314
315
316
317
318
319 
                                                COMM
320
321 
                                                        4
322 
                                                        0
323
324
325
326 
                                                agent_comm_out
327
328 
                                                        4
329 
                                                        0
330
331
332
333
334
335 
                                                DATA
336
337 
                                                        31
338 
                                                        0
339
340
341
342 
                                                agent_data_out
343
344 
                                                        31
345 
                                                        0
346
347
348
349
350
351 
                                                EMPTY
352
353 
                                                        0
354 
                                                        0
355
356
357
358 
                                                agent_empty_out
359
360 
                                                        0
361 
                                                        0
362
363
364
365
366
367 
                                                FULL
368
369 
                                                        0
370 
                                                        0
371
372
373
374 
                                                agent_full_out
375
376 
                                                        0
377 
                                                        0
378
379
380
381
382
383 
                                                ONE_D
384
385 
                                                        0
386 
                                                        0
387
388
389
390 
                                                agent_one_d_out
391
392 
                                                        0
393 
                                                        0
394
395
396
397
398
399 
                                                ONE_P
400
401 
                                                        0
402 
                                                        0
403
404
405
406 
                                                agent_one_p_out
407
408 
                                                        0
409 
                                                        0
410
411
412
413
414 
                        8
415 
                        little
416
417
418 
                        rst_n
419
420
421
422 
                        false
423
424
425
426 
                                                RESETn
427
428 
                                                        0
429 
                                                        0
430
431
432
433 
                                                rst_n
434
435 
                                                        0
436 
                                                        0
437
438
439
440
441 
                        8
442 
                        little
443
444
445 
                        clocks
446 
                        HIBI clock input
447
448
449
450 
                        false
451
452
453
454 
                                                AGENT_CLK
455
456 
                                                        0
457 
                                                        0
458
459
460
461 
                                                agent_clk
462
463 
                                                        0
464 
                                                        0
465
466
467
468
469
470 
                                                AGENT_SYNC_CLK
471
472 
                                                        0
473 
                                                        0
474
475
476
477 
                                                agent_sync_clk
478
479 
                                                        0
480 
                                                        0
481
482
483
484
485
486 
                                                BUS_CLK
487
488 
                                                        0
489 
                                                        0
490
491
492
493 
                                                bus_clk
494
495 
                                                        0
496 
                                                        0
497
498
499
500
501
502 
                                                BUS_SYNC_CLK
503
504 
                                                        0
505 
                                                        0
506
507
508
509 
                                                bus_sync_clk
510
511 
                                                        0
512 
                                                        0
513
514
515
516
517 
                        8
518 
                        little
519
520
521
522
523 
                        hibi_ip_master_channel
524 
                        ip_mMaster
525 
                        bus_mSlave
526
527
528 
                        hibi_ip_slave_channel
529 
                        ip_mSlave
530 
                        bus_mMaster
531
532
533
534
535
536 
                                rtl
537 
                                VHDL::
538
539 
                                        hdlSources
540
541
542 
                                        fifo_rtl
543
544
545
546
547
548 
                                agent_av_in
549
550 
                                        in
551
552 
                                                0
553 
                                                0
554
555
556 
                                                '0'
557
558
559
560
561
562 
                                agent_av_out
563
564 
                                        out
565
566
567
568
569 
                                agent_clk
570
571 
                                        in
572
573 
                                                0
574 
                                                0
575
576
577
578
579
580 
                                agent_comm_in
581
582 
                                        in
583
584 
                                                4
585 
                                                0
586
587
588 
                                                (others => '0')
589
590
591
592
593
594 
                                agent_comm_out
595
596 
                                        out
597
598 
                                                4
599 
                                                0
600
601
602
603
604
605 
                                agent_data_in
606
607 
                                        in
608
609 
                                                31
610 
                                                0
611
612
613 
                                                (others => '0')
614
615
616
617
618
619 
                                agent_data_out
620
621 
                                        out
622
623 
                                                31
624 
                                                0
625
626
627
628
629
630 
                                agent_empty_out
631
632 
                                        out
633
634 
                                                0
635 
                                                0
636
637
638
639
640
641 
                                agent_full_out
642
643 
                                        out
644
645 
                                                0
646 
                                                0
647
648
649
650
651
652 
                                agent_one_d_out
653
654 
                                        out
655
656 
                                                0
657 
                                                0
658
659
660
661
662
663 
                                agent_one_p_out
664
665 
                                        out
666
667 
                                                0
668 
                                                0
669
670
671
672
673
674 
                                agent_re_in
675
676 
                                        in
677
678 
                                                0
679 
                                                0
680
681
682 
                                                '0'
683
684
685
686
687
688 
                                agent_sync_clk
689
690 
                                        in
691
692
693
694
695 
                                agent_we_in
696
697 
                                        in
698
699 
                                                0
700 
                                                0
701
702
703 
                                                '0'
704
705
706
707
708
709 
                                bus_av_in
710
711 
                                        in
712
713 
                                                0
714 
                                                0
715
716
717 
                                                '0'
718
719
720
721
722
723 
                                bus_av_out
724
725 
                                        out
726
727 
                                                0
728 
                                                0
729
730
731
732
733
734 
                                bus_clk
735
736 
                                        in
737
738 
                                                0
739 
                                                0
740
741
742
743
744
745 
                                bus_comm_in
746
747 
                                        in
748
749 
                                                4
750 
                                                0
751
752
753 
                                                (others => '0')
754
755
756
757
758
759 
                                bus_comm_out
760
761 
                                        out
762
763 
                                                4
764 
                                                0
765
766
767
768
769
770 
                                bus_data_in
771
772 
                                        in
773
774 
                                                31
775 
                                                0
776
777
778 
                                                (others => '0')
779
780
781
782
783
784 
                                bus_data_out
785
786 
                                        out
787
788 
                                                31
789 
                                                0
790
791
792
793
794
795 
                                bus_full_in
796
797 
                                        in
798
799 
                                                '0'
800
801
802
803
804
805 
                                bus_full_out
806
807 
                                        out
808
809 
                                                0
810 
                                                0
811
812
813
814
815
816 
                                bus_lock_in
817
818 
                                        in
819
820 
                                                0
821 
                                                0
822
823
824 
                                                '0'
825
826
827
828
829
830 
                                bus_lock_out
831
832 
                                        out
833
834 
                                                0
835 
                                                0
836
837
838
839
840
841 
                                bus_sync_clk
842
843 
                                        in
844
845 
                                                '0'
846
847
848
849
850
851 
                                debug_in
852
853 
                                        in
854
855
856 
                                                        std_logic_vector
857 
                                                        IEEE.std_logic_1164.all
858 
                                                        rtl
859
860
861
862 
                                                (others => '0')
863
864
865
866
867
868
869
870 
                                debug_out
871
872 
                                        out
873
874
875 
                                                        std_logic_vector
876 
                                                        IEEE.std_logic_1164.all
877 
                                                        rtl
878
879
880
881
882
883
884
885
886 
                                rst_n
887
888 
                                        in
889
890 
                                                0
891 
                                                0
892
893
894
895
896
897
898
899 
                                addr_g
900 
                                addressing settings: unique for each wrapper
901 
                                46
902
903
904 
                                addr_limit_g
905 
                                Upper address boundary
906 
                                0
907
908
909 
                                addr_width_g
910 
                                HIBI address width
911 
                                32
912
913
914 
                                arb_type_g
915 
                                Arbitration type 0 round-robin, 1 priority, 2 combined, 3 DAA. Ensure that all wrappers in a segment agree on arb_type
916 
                                0
917
918
919 
                                cfg_re_g
920 
                                 enable reading config
921 
                                0
922
923
924 
                                cfg_we_g
925 
                                enable writing config
926 
                                0
927
928
929 
                                comm_width_g
930 
                                HIBI communication width (HIBI v.2=3, v.3 = 5 bits)
931 
                                5
932
933
934 
                                counter_width_g
935 
                                greater than or equal (n_agents, max_send...)
936 
                                7
937
938
939 
                                data_width_g
940 
                                HIBI data width (less than or equal)
941 
                                32
942
943
944 
                                debug_width_g
945 
                                For special monitors
946 
                                0
947
948
949 
                                fifo_sel_g
950 
                                fifo_sel: 0 synch multiclk, 1 basic GALS,  2 Gray FIFO (depth=2^n!), 3 mixed clock pausible ( use 0 for synchronous systems)
951 
                                0
952
953
954 
                                id_g
955 
                                 used instead of addr in recfg
956 
                                5
957
958
959 
                                id_max_g
960 
                                Only for bridges+cfg, zero for others!
961 
                                0
962
963
964 
                                id_min_g
965 
                                Only for bridges+cfg, zero for others!
966 
                                0
967
968
969 
                                id_width_g
970 
                                gte(log2(id_g))
971 
                                4
972
973
974 
                                inv_addr_en_g
975 
                                Only for bridges
976 
                                0
977
978
979 
                                keep_slot_g
980 
                                for TDMA
981 
                                0
982
983
984 
                                max_send_g
985 
                                in words. Max_send can be wrapper-specific.
986 
                                50
987
988
989 
                                n_agents_g
990 
                                Number of agents within one segment. Ensure that all wrappers in a segment agree on n_agents
991 
                                4
992
993
994 
                                n_cfg_pages_g
995 
                                Having multiple pages allows fast reconfig. Note that cfg memory initialization is done with separate package if you have many time slots or configuration pages
996 
                                0
997
998
999 
                                n_extra_params_g
1000 
                                app-specific registers
1001 
                                0
1002
1003
1004 
                                n_time_slots_g
1005 
                                TDMA is enabled by setting n_time_slots > 0
1006 
                                0
1007
1008
1009 
                                prior_g
1010 
                                lte n_agents
1011 
                                2
1012
1013
1014 
                                rel_agent_freq_g
1015 
                                Synch_multiclk FIFOs must know the ratio of frequencies
1016 
                                1
1017
1018
1019 
                                rel_bus_freq_g
1020 
                                Synch_multiclk FIFOs must know the ratio of frequencies
1021 
                                1
1022
1023
1024 
                                rx_fifo_depth_g
1025 
                                All FIFO depths are given in words. Allowed values 0,2,3... words.
1026 
                                5
1027
1028
1029 
                                rx_msg_fifo_depth_g
1030 
                                All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
1031 
                                5
1032
1033
1034 
                                separate_addr_g
1035 
                                Transmits addr in parallel with data
1036 
                                0
1037
1038
1039 
                                tx_fifo_depth_g
1040 
                                All FIFO depths are given in words. Allowed values 0,2,3... words.
1041 
                                5
1042
1043
1044 
                                tx_msg_fifo_depth_g
1045 
                                All FIFO depths are given in words. Allowed values 0,2,3... words.Prefix msg refers to hi-prior data
1046 
                                5
1047
1048
1049
1050
1051
1052 
                        hdlSources
1053 
                        VHDL for HIBI wrapper r4. Note that FIFOs are in different directory so that other NoCs can use them also.
1054
1055 
                                ../vhd/hibiv3_pkg.vhd
1056 
                                vhdlSource
1057 
                                false
1058 
                                hibi
1059
1060
1061 
                                ../vhd/fifo_mux_rd.vhd
1062 
                                vhdlSource
1063 
                                false
1064 
                                hibi
1065
1066
1067 
                                ../vhd/hibi_wrapper_r1.vhd
1068 
                                vhdlSource
1069 
                                false
1070 
                                hibi
1071
1072
1073 
                                ../vhd/hibi_wrapper_r4.vhd
1074 
                                vhdlSource
1075 
                                false
1076 
                                hibi
1077
1078
1079 
                                ../vhd/lfsr.vhd
1080 
                                vhdlSource
1081 
                                false
1082 
                                hibi
1083
1084
1085 
                                ../vhd/receiver.vhd
1086 
                                vhdlSource
1087 
                                false
1088 
                                hibi
1089
1090
1091 
                                ../vhd/rx_control.vhd
1092 
                                vhdlSource
1093 
                                false
1094 
                                hibi
1095
1096
1097 
                                ../vhd/transmitter.vhd
1098 
                                vhdlSource
1099 
                                false
1100 
                                hibi
1101
1102
1103 
                                ../vhd/tx_control.vhd
1104 
                                vhdlSource
1105 
                                false
1106 
                                hibi
1107
1108
1109 
                                ../vhd/addr_decoder.vhd
1110 
                                vhdlSource
1111 
                                false
1112 
                                hibi
1113
1114
1115 
                                ../vhd/cfg_init_pkg.vhd
1116 
                                vhdlSource
1117 
                                false
1118 
                                hibi
1119
1120
1121 
                                ../vhd/cfg_mem.vhd
1122 
                                vhdlSource
1123 
                                false
1124 
                                hibi
1125
1126
1127 
                                ../vhd/dyn_arb.vhd
1128 
                                vhdlSource
1129 
                                false
1130 
                                hibi
1131
1132
1133 
                                ../vhd/fifo_demux_wr.vhd
1134 
                                vhdlSource
1135 
                                false
1136 
                                hibi
1137
1138
1139 
                                ../vhd/double_fifo_mux_rd.vhd
1140 
                                vhdlSource
1141 
                                false
1142 
                                hibi
1143
1144
1145 
                                ../vhd/double_fifo_demux_wr.vhd
1146 
                                vhdlSource
1147 
                                false
1148 
                                hibi
1149
1150
1151 
                                vhdlSource
1152 
                                Default file builders
1153 
                                vcom
1154 
                                 -work hibi -check_synthesis -quiet
1155 
                                false
1156
1157 
                        ../../../../ip.hwp.storage/fifos
1158
1159
1160 
                        fifo_rtl
1161 
                        Various FIFO buffers and synchronizers.
1162
1163 
                                ../../../../ip.hwp.storage/fifos/fifo/1.0/vhd/fifo.vhd
1164 
                                vhdlSource
1165 
                                false
1166 
                                hibi
1167
1168
1169 
                                ../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/mixed_clk_fifo_v3.vhd
1170 
                                vhdlSource
1171 
                                false
1172 
                                hibi
1173
1174
1175 
                                ../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/multiclk_fifo.vhd
1176 
                                vhdlSource
1177 
                                false
1178 
                                hibi
1179
1180
1181 
                                ../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/re_pulse_synchronizer.vhd
1182 
                                vhdlSource
1183 
                                false
1184 
                                hibi
1185
1186
1187 
                                ../../../../ip.hwp.storage/fifos/multiclk_fifo/1.0/vhd/we_pulse_synchronizer.vhd
1188 
                                vhdlSource
1189 
                                false
1190 
                                hibi
1191
1192
1193 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
1194 
                                vhdlSource
1195 
                                false
1196 
                                hibi
1197
1198
1199 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
1200 
                                vhdlSource
1201 
                                false
1202 
                                hibi
1203
1204
1205 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
1206 
                                vhdlSource
1207 
                                false
1208 
                                hibi
1209
1210
1211 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
1212 
                                vhdlSource
1213 
                                false
1214 
                                hibi
1215
1216
1217 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
1218 
                                vhdlSource
1219 
                                false
1220 
                                hibi
1221
1222
1223 
                                ../../../../ip.hwp.storage/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
1224 
                                vhdlSource
1225 
                                false
1226 
                                hibi
1227
1228
1229 
                                vhdlSource
1230 
                                vcom
1231 
                                 -work hibi -check_synthesis -quiet
1232 
                                false
1233
1234
1235
1236 
                        doc
1237 
                        Documentation for HIBI v3.0.
1238
1239 
                                ../doc/clock_distribution_readme.txt
1240 
                                ASCII
1241 
                                false
1242
1243
1244 
                                ../doc/hibi_v2_to_v3.pptx
1245 
                                powerPoint
1246 
                                false
1247
1248
1249 
                                ../doc/hibi_v3_datasheet_2011_11_15.pdf
1250 
                                pdf
1251 
                                false
1252
1253
1254 
                                ../vhd/structure.txt
1255 
                                ASCII
1256 
                                false
1257
1258
1259
1260
1261
1262
1263 
                                IP
1264 
                                Parameterizable
1265
1266
1267
1268

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