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#!/bin/sh
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#
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# Compiles all VHDL files and special SystemC test suite.
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#
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# Test suite supports both normal mode and simultaneous
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# addr+data (=sad), as well as all commands of HIBI v.3.
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# Moreover, interface revisions r3 and r4 can be tested.
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#
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# Lasse Lehtonen, September 2011
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# Define the path to hibi root directory (relative to your current directory)
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root="."
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# These external components are all relative to that "root"
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mem_dir="$root/../../../ip.hwp.storage"
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tb_dir="$root/tb/sad_tb"
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# Define library names
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msimlibs="msim_libs"
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vhdlib="$msimlibs/vhd_lib"
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n4_sclib="$msimlibs/norm4_sc_lib"
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s4_sclib="$msimlibs/sad4_sc_lib"
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n3_sclib="$msimlibs/norm3_sc_lib"
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s3_sclib="$msimlibs/sad3_sc_lib"
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# Define macros compilation commands and flags
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com_vhdl="vcom -check_synthesis -lint -pedanticerrors -novopt -work $vhdlib -quiet"
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# Flags define normal vs. sad mode, and r3 vs. r4
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com_sv_s4="sccom -DHIBI_IN_SAD_MODE -O3 -I $$(tb_dir) -work $s4_sclib -nologo -Wall -incr"
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com_sv_n4="sccom -O3 -I $$(tb_dir) -work $n4_sclib -nologo -Wall -incr"
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com_sv_s3="sccom -DUSE_R3_WRAPPERS -DHIBI_IN_SAD_MODE -O3 -I $$(tb_dir) -work $s3_sclib -nologo -Wall -incr"
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com_sv_n3="sccom -DUSE_R3_WRAPPERS -O3 -I $$(tb_dir) -work $n3_sclib -nologo -Wall -incr"
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# Check if directories exist, and create them if necessary
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echo "##"
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if [ -d "$msimlibs" ]
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then
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echo "## 1/5 Modelsim working library directory $msimlibs already exists"
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else
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echo "## 1/5 Creating working libraries for Modelsim in directory $msimlibs"
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mkdir $msimlibs
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fi
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if [ -d "$vhdlib" ]
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then
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echo "## $vhdlib already exists"
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else
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echo "## Creating $vhdlib"
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vlib $vhdlib
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fi
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if [ -d "$n4_sclib" ]
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then
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echo "## $n4_sclib already exists"
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else
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echo "## Creating $n4_sclib"
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vlib $n4_sclib
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fi
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if [ -d "$s4_sclib" ]
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then
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echo "## $s4_sclib already exists"
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else
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echo "## Creating $s4_sclib"
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vlib $s4_sclib
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fi
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if [ -d "$n3_sclib" ]
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then
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echo "## $n3_sclib already exists"
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else
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echo "## Creating $n3_sclib"
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vlib $n3_sclib
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fi
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if [ -d "$s3_sclib" ]
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then
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echo "## $s3_sclib already present"
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else
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echo "## Creating $s3_sclib"
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vlib $s3_sclib
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fi
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echo "##"
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echo "## 2/5 Compiling VHDL source files"
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echo "##"
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#
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# FIFOs
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#
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$com_vhdl $root/$mem_dir/fifos/fifo/1.0/vhd/fifo.vhd
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$com_vhdl $root/$mem_dir/fifos/multiclk_fifo/1.0/vhd//multiclk_fifo.vhd
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$com_vhdl $root/$mem_dir/fifos/multiclk_fifo/1.0/vhd//re_pulse_synchronizer.vhd
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$com_vhdl $root/$mem_dir/fifos/multiclk_fifo/1.0/vhd//we_pulse_synchronizer.vhd
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$com_vhdl $root/$mem_dir/fifos/multiclk_fifo/1.0/vhd//mixed_clk_fifo_v3.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_read_in.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_read_out.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_read_top.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_we_in.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_we_out.vhd
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$com_vhdl $root/$mem_dir/fifos/synchronizer/1.0/vhd/aif_we_top.vhd
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$com_vhdl $root/$mem_dir/fifos/gray_fifo/1.0/vhd/async_dpram.vhd
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$com_vhdl $root/$mem_dir/fifos/gray_fifo/1.0/vhd/async_dpram_generic.vhd
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$com_vhdl $root/$mem_dir/fifos/gray_fifo/1.0/vhd/gray.vhd
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$com_vhdl $root/$mem_dir/fifos/gray_fifo/1.0/vhd/cdc_fifo_ctrl.vhd
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$com_vhdl $root/$mem_dir/fifos/gray_fifo/1.0/vhd/cdc_fifo.vhd
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#
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# HIBI files
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#
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$com_vhdl $root/vhd/hibiv3_pkg.vhd
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$com_vhdl $root/vhd/fifo_demux_wr.vhd
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$com_vhdl $root/vhd/fifo_mux_rd.vhd
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$com_vhdl $root/vhd/double_fifo_demux_wr.vhd
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$com_vhdl $root/vhd/double_fifo_mux_rd.vhd
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$com_vhdl $root/vhd/addr_decoder.vhd
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$com_vhdl $root/vhd/rx_control.vhd
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$com_vhdl $root/vhd/receiver.vhd
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$com_vhdl $root/vhd/cfg_init_pkg.vhd
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$com_vhdl $root/vhd/cfg_mem.vhd
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$com_vhdl $root/vhd/lfsr.vhd
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$com_vhdl $root/vhd/dyn_arb.vhd
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$com_vhdl $root/vhd/tx_control.vhd
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$com_vhdl $root/vhd/transmitter.vhd
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$com_vhdl $root/vhd/hibi_wrapper_r1.vhd
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$com_vhdl $root/vhd/hibi_wrapper_r4.vhd
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$com_vhdl $root/vhd/hibi_bridge_v2.vhd
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#$com_vhdl $root/vhd/addr_data_demux_write.vhd
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#$com_vhdl $root/vhd/addr_data_mux_read.vhd
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#$com_vhdl $root/vhd/hibi_wrapper_r2.vhd
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$com_vhdl $root/vhd/addr_data_demux_read.vhd
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$com_vhdl $root/vhd/addr_data_mux_write.vhd
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$com_vhdl $root/vhd/hibi_wrapper_r3.vhd
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echo "##"
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echo "## 3/5 Compiling TB source files (VHDL + SystemC)"
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echo "##"
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$com_vhdl $root/$tb_dir/hibiv3_r4.vhd
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$com_vhdl $root/$tb_dir/hibiv3_r3.vhd
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$com_sv_n4 $root/$tb_dir/main.cc
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$com_sv_s4 $root/$tb_dir/main.cc
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$com_sv_n3 $root/$tb_dir/main.cc
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$com_sv_s3 $root/$tb_dir/main.cc
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# There may appear couple of warnings "not debuggable" which should do not harm
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echo "##"
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echo "## 4/5Linking"
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echo "##"
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sccom -link -work $s4_sclib -lib $s4_sclib -lib $vhdlib -nologo
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sccom -link -work $n4_sclib -lib $n4_sclib -lib $vhdlib -nologo
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sccom -link -work $s3_sclib -lib $s3_sclib -lib $vhdlib -nologo
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sccom -link -work $n3_sclib -lib $n3_sclib -lib $vhdlib -nologo
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echo "##"
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echo "## 5/5 All done"
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echo "##"
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echo "## To simulate: "
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echo "## normal mode, R4: vsim -novopt -lib $n4_sclib -L $vhdlib sc_main &"
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echo "## sad mode, R4 : vsim -novopt -lib $s4_sclib -L $vhdlib sc_main &"
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echo "## normal mode, R3: vsim -novopt -lib $n3_sclib -L $vhdlib sc_main &"
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echo "## sad mode, R3 : vsim -novopt -lib $s3_sclib -L $vhdlib sc_main &"
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echo "##"
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echo "## Run the simulation until the message SAD HIBI TESTBENCH FINISHED appears, e.g. 3 ms"
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echo "## Order (from fastest to slowest): "
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echo "## sad_r4 (1.8 ms), sad_r3 (2 ms), norm (2.5ms), and norm_r4 (2.7ms) (2011-09-06)"
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