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-------------------------------------------------------------------------------
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-- file : hibi_orbus_small.vhd
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-- description : Bus resolution is done by ORring all the inputs. E.g.
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-- data_out <= data_0_in or data_1_in or...
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-- author : Erno Salminen
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-- date : 2012-03-07
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-- modified :
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the impliedlk
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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--use work.hibiv3_pkg.all; -- hibi v3 commands
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entity hibi_orbus_small is
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generic (
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data_width_g : integer := 32;
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comm_width_g : integer := 5
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);
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port (
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bus_av_out : out std_logic;
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bus_data_out : out std_logic_vector(data_width_g-1 downto 0);
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bus_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_out : out std_logic;
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bus_full_out : out std_logic;
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bus_av_0_in : in std_logic;
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bus_data_0_in : in std_logic_vector(data_width_g-1 downto 0);
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bus_comm_0_in : in std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_0_in : in std_logic;
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bus_full_0_in : in std_logic;
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bus_av_1_in : in std_logic;
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bus_data_1_in : in std_logic_vector(data_width_g-1 downto 0);
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bus_comm_1_in : in std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_1_in : in std_logic;
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bus_full_1_in : in std_logic;
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bus_av_2_in : in std_logic;
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bus_data_2_in : in std_logic_vector(data_width_g-1 downto 0);
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bus_comm_2_in : in std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_2_in : in std_logic;
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bus_full_2_in : in std_logic;
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bus_av_3_in : in std_logic;
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bus_data_3_in : in std_logic_vector(data_width_g-1 downto 0);
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bus_comm_3_in : in std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_3_in : in std_logic;
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bus_full_3_in : in std_logic
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);
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end hibi_orbus_small;
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architecture structural of hibi_orbus_small is
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begin -- structural
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-- continuous assignments
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bus_av_out <= bus_av_0_in or bus_av_1_in or bus_av_2_in or bus_av_3_in ;
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bus_data_out <= bus_data_0_in or bus_data_1_in or bus_data_2_in or bus_data_3_in;
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bus_comm_out <= bus_comm_0_in or bus_comm_1_in or bus_comm_2_in or bus_comm_3_in;
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bus_lock_out <= bus_lock_0_in or bus_lock_1_in or bus_lock_2_in or bus_lock_3_in;
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bus_full_out <= bus_full_0_in or bus_full_1_in or bus_full_2_in or bus_full_3_in;
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end structural;
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