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-------------------------------------------------------------------------------
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-- File : hibi_wrapper.vhdl
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-- Description : A wrapper component to interconnect resources in
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-- System-on-chips.
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-- Interface revision r1 is the 'base' for all HIBI wrappers:
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-- - separate IP interface for regular and hi-prior data
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-- - IP writes/gets addr and data sequentially
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-- Implementation can be chosen with generics.
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-- Author : Erno Salminen
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-- Project : Nocbench & Funbase
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-- Design :
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-- Date : 01.04.2011 (nased on HIBI v.2)
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-- Modified :
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--
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This file is part of HIBI
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use work.hibiv3_pkg.all;
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entity hibi_wrapper_r1 is
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generic (
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-- Note: n_ = number of,
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-- lte = less than or equal,
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-- gte = greater than or equal
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-- Structural settings.
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-- All widths are given in bits
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addr_width_g : integer;
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data_width_g : integer;
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comm_width_g : integer;
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counter_width_g : integer; -- gte (n_agents, max_send...)
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debug_width_g : integer := 0; -- for special monitors
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-- All FIFO depths are given in words
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-- Allowed values 0,2,3... words.
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-- Prefix msg refers to hi-prior data
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rx_fifo_depth_g : integer := 5;
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tx_fifo_depth_g : integer := 5;
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rx_msg_fifo_depth_g : integer := 5;
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tx_msg_fifo_depth_g : integer := 5;
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-- Clocking and synchronization
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-- fifo_sel: 0 synch multiclk, 1 basic GALS,
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-- 2 Gray FIFO (depth=2^n), 3 mixed clock pausible
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fifo_sel_g : integer := 0; -- use 0 for synchronous systems
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-- E.g. Synch_multiclk FIFOs must know the ratio of frequencies
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rel_agent_freq_g : integer := 1;
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rel_bus_freq_g : integer := 1;
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-- Functional: addressing settings
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addr_g : integer := 46; -- unique for each wrapper
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inv_addr_en_g : integer := 0; -- only for bridges
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-- Functional: arbitration
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-- arb_type=0 round-robin, 1 priority, 2 combined, 3 DAA.
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-- TDMA is enabled by setting n_time_slots > 0
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-- Ensure that all wrappers in a segment agree on arb_type,
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-- n_agents, and n_slots. Max_send can be wrapper-specific.
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arb_type_g : integer := 0; -- select 0-3
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n_agents_g : integer := 4; -- within one segment
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prior_g : integer := 2; -- lte n_agents
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max_send_g : integer := 50; -- in words, 0 means unlimited
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n_time_slots_g : integer := 0; -- for TDMA
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keep_slot_g : integer := 1; -- for TDMA
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-- Func/Stuctural: (Run-time re)configuration memory
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id_g : integer := 5; -- used instead of addr in recfg
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id_width_g : integer := 4; -- gte(log2(id_g))
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cfg_re_g : integer := 0; -- enable reading config
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cfg_we_g : integer := 0; -- enable writing config
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n_extra_params_g : integer := 0; -- app-specific registers
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n_cfg_pages_g : integer := 1; -- multiple pages allows fast reconfig
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-- Note that cfg memory initialization is done with separate
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-- package if you have many time slots or configuration pages
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-- NEW for HIBI v.3
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id_min_g : integer := 0; -- Only for bridges+cfg, zero for others!
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id_max_g : integer := 0; -- Only for bridges+cfg, zero for others!
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addr_limit_g : integer := 0; -- Uppermost addr of a wrapper/bridge
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separate_addr_g : integer := 0 -- Transmits addr in parallel with data
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);
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port (
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bus_clk : in std_logic;
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agent_clk : in std_logic;
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-- pulsed clocks as used in pausible clock scheme
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-- IF fifo 1 and fast synch is used, sync clocks is used as the
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-- HIBI synch clock
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bus_sync_clk : in std_logic;
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agent_sync_clk : in std_logic;
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rst_n : in std_logic;
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bus_av_in : in std_logic;
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bus_data_in : in std_logic_vector (data_width_g-1 downto 0);
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bus_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
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bus_full_in : in std_logic;
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bus_lock_in : in std_logic;
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agent_av_in : in std_logic;
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agent_data_in : in std_logic_vector (data_width_g-1 downto 0);
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agent_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
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agent_we_in : in std_logic;
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agent_full_out : out std_logic;
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agent_one_p_out : out std_logic;
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agent_msg_av_in : in std_logic;
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agent_msg_data_in : in std_logic_vector (data_width_g-1 downto 0);
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agent_msg_comm_in : in std_logic_vector (comm_width_g-1 downto 0);
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agent_msg_we_in : in std_logic;
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agent_msg_re_in : in std_logic;
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bus_av_out : out std_logic;
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bus_data_out : out std_logic_vector (data_width_g-1 downto 0);
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bus_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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bus_lock_out : out std_logic;
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bus_full_out : out std_logic;
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agent_av_out : out std_logic;
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agent_data_out : out std_logic_vector (data_width_g-1 downto 0);
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agent_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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agent_empty_out : out std_logic;
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agent_one_d_out : out std_logic;
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agent_re_in : in std_logic;
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agent_msg_av_out : out std_logic;
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agent_msg_data_out : out std_logic_vector (data_width_g-1 downto 0);
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agent_msg_comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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agent_msg_empty_out : out std_logic;
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agent_msg_one_d_out : out std_logic;
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agent_msg_full_out : out std_logic;
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agent_msg_one_p_out : out std_logic
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-- synthesis translate_off
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;
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debug_out : out std_logic_vector(debug_width_g-1 downto 0);
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debug_in : in std_logic_vector(debug_width_g-1 downto 0)
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-- synthesis translate_on
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);
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end hibi_wrapper_r1;
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architecture structural of hibi_wrapper_r1 is
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-- Structure
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-- 1. Control logic for both transmitting (tx) and receiving (rx).
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-- 2. FIFOs for tx and rx. Actually, there can be 2 FIFOs in each direction:
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-- for regular and high-priority data.
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-- IP connects to the FIFOS.
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-- Controllers are between FIFOs and the bus. Controllers are connected
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-- together for configuring and reading the config.
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component transmitter is
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generic (
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id_g : integer;
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addr_g : integer;
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id_width_g : integer;
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data_width_g : integer;
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addr_width_g : integer;
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comm_width_g : integer;
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counter_width_g : integer;
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cfg_addr_width_g : integer;
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prior_g : integer;
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inv_addr_en_g : integer;
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max_send_g : integer;
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arb_type_g : integer;
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n_agents_g : integer;
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n_cfg_pages_g : integer;
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n_time_slots_g : integer;
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keep_slot_g : integer;
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n_extra_params_g : integer;
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cfg_we_g : integer;
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cfg_re_g : integer;
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separate_addr_g : integer;
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debug_width_g : integer);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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lock_in : in std_logic;
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full_in : in std_logic;
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cfg_data_in : in std_logic_vector
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(data_width_g-1-(separate_addr_g*addr_width_g) downto 0);
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cfg_addr_in : in std_logic_vector(cfg_addr_width_g -1 downto 0);
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cfg_ret_addr_in : in std_logic_vector(addr_width_g -1 downto 0);
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cfg_re_in : in std_logic;
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cfg_we_in : in std_logic;
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av_in : in std_logic;
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data_in : in std_logic_vector(data_width_g-1 downto 0);
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comm_in : in std_logic_vector(comm_width_g-1 downto 0);
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empty_in : in std_logic;
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one_d_in : in std_logic;
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av_out : out std_logic;
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data_out : out std_logic_vector(data_width_g-1 downto 0);
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comm_out : out std_logic_vector(comm_width_g-1 downto 0);
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lock_out : out std_logic;
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cfg_rd_rdy_out : out std_logic;
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re_out : out std_logic
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-- synthesis translate_off
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;
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debug_out : out std_logic_vector(debug_width_g-1 downto 0);
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debug_in : in std_logic_vector(debug_width_g-1 downto 0)
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-- synthesis translate_on
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);
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end component transmitter;
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component double_fifo_mux_rd
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generic (
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fifo_sel_g : integer;
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re_freq_g : integer;
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we_freq_g : integer;
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depth_0_g : integer;
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depth_1_g : integer;
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data_width_g : integer;
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debug_width_g : integer;
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comm_width_g : integer;
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separate_addr_g : integer
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);
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port (
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clk_re : in std_logic;
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clk_we : in std_logic;
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clk_re_pls : in std_logic;
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clk_we_pls : in std_logic;
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rst_n : in std_logic;
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av_0_in : in std_logic;
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data_0_in : in std_logic_vector (data_width_g-1 downto 0);
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comm_0_in : in std_logic_vector (comm_width_g-1 downto 0);
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we_0_in : in std_logic;
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one_p_0_out : out std_logic;
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full_0_out : out std_logic;
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av_1_in : in std_logic;
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data_1_in : in std_logic_vector (data_width_g-1 downto 0);
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comm_1_in : in std_logic_vector (comm_width_g-1 downto 0);
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we_1_in : in std_logic;
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full_1_out : out std_logic;
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one_p_1_out : out std_logic;
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re_in : in std_logic;
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av_out : out std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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comm_out : out std_logic_vector (comm_width_g-1 downto 0);
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empty_out : out std_logic;
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one_d_out : out std_logic;
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debug_out : out std_logic_vector(debug_width_g downto 0)
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);
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end component double_fifo_mux_rd;
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component receiver
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generic (
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id_g : integer;
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id_min_g : integer := 0; -- Only for bridges, zero for others!
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id_max_g : integer := 0; -- Only for bridges, zero for others!
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addr_base_g : integer;
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addr_limit_g : integer := 0;
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id_width_g : integer;
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data_width_g : integer;
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addr_width_g : integer;
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cfg_addr_width_g : integer;
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cfg_re_g : integer;
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cfg_we_g : integer;
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inv_addr_en_g : integer;
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separate_addr_g : integer := 0
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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av_in : in std_logic;
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data_in : in std_logic_vector(data_width_g-1 downto 0);
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comm_in : in std_logic_vector(comm_width_c-1 downto 0);
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311 |
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cfg_rd_rdy_in : in std_logic;
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312 |
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av_0_out : out std_logic;
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data_0_out : out std_logic_vector(data_width_g-1 downto 0);
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comm_0_out : out std_logic_vector(comm_width_c-1 downto 0);
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we_0_out : out std_logic;
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full_0_in : in std_logic;
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one_p_0_in : in std_logic;
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319 |
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av_1_out : out std_logic;
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data_1_out : out std_logic_vector(data_width_g-1 downto 0);
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comm_1_out : out std_logic_vector(comm_width_c-1 downto 0);
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we_1_out : out std_logic;
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324 |
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full_1_in : in std_logic;
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325 |
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one_p_1_in : in std_logic;
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326 |
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327 |
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bus_full_in : in std_logic;
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cfg_we_out : out std_logic;
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329 |
|
|
cfg_re_out : out std_logic;
|
330 |
|
|
cfg_data_out : out std_logic_vector
|
331 |
|
|
(data_width_g-1-(separate_addr_g*addr_width_g) downto 0);
|
332 |
|
|
cfg_addr_out : out std_logic_vector(cfg_addr_width_g -1 downto 0);
|
333 |
|
|
cfg_ret_addr_out : out std_logic_vector(addr_width_g -1 downto 0);
|
334 |
|
|
full_out : out std_logic
|
335 |
|
|
);
|
336 |
|
|
end component receiver;
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
component double_fifo_demux_wr
|
341 |
|
|
generic (
|
342 |
|
|
fifo_sel_g : integer;
|
343 |
|
|
re_freq_g : integer;
|
344 |
|
|
we_freq_g : integer;
|
345 |
|
|
depth_0_g : integer;
|
346 |
|
|
depth_1_g : integer;
|
347 |
|
|
data_width_g : integer;
|
348 |
|
|
debug_width_g : integer;
|
349 |
|
|
comm_width_g : integer
|
350 |
|
|
);
|
351 |
|
|
port (
|
352 |
|
|
clk_re : in std_logic;
|
353 |
|
|
clk_we : in std_logic;
|
354 |
|
|
clk_re_pls : in std_logic;
|
355 |
|
|
clk_we_pls : in std_logic;
|
356 |
|
|
rst_n : in std_logic;
|
357 |
|
|
|
358 |
|
|
av_0_in : in std_logic;
|
359 |
|
|
data_0_in : in std_logic_vector (data_width_g-1 downto 0);
|
360 |
|
|
comm_0_in : in std_logic_vector (comm_width_g-1 downto 0);
|
361 |
|
|
we_0_in : in std_logic;
|
362 |
|
|
one_p_0_out : out std_logic;
|
363 |
|
|
full_0_out : out std_logic;
|
364 |
|
|
|
365 |
|
|
av_1_in : in std_logic;
|
366 |
|
|
data_1_in : in std_logic_vector (data_width_g-1 downto 0);
|
367 |
|
|
comm_1_in : in std_logic_vector (comm_width_g-1 downto 0);
|
368 |
|
|
we_1_in : in std_logic;
|
369 |
|
|
one_p_1_out : out std_logic;
|
370 |
|
|
full_1_out : out std_logic;
|
371 |
|
|
|
372 |
|
|
re_0_in : in std_logic;
|
373 |
|
|
av_0_out : out std_logic;
|
374 |
|
|
data_0_out : out std_logic_vector (data_width_g-1 downto 0);
|
375 |
|
|
comm_0_out : out std_logic_vector (comm_width_g-1 downto 0);
|
376 |
|
|
empty_0_out : out std_logic;
|
377 |
|
|
one_d_0_out : out std_logic;
|
378 |
|
|
|
379 |
|
|
re_1_in : in std_logic;
|
380 |
|
|
av_1_out : out std_logic;
|
381 |
|
|
data_1_out : out std_logic_vector (data_width_g-1 downto 0);
|
382 |
|
|
comm_1_out : out std_logic_vector (comm_width_g-1 downto 0);
|
383 |
|
|
empty_1_out : out std_logic;
|
384 |
|
|
one_d_1_out : out std_logic;
|
385 |
|
|
debug_out : out std_logic_vector(debug_width_g downto 0)
|
386 |
|
|
);
|
387 |
|
|
end component double_fifo_demux_wr;
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
-- Calculate minimum of 1 and "value"
|
391 |
|
|
-- Required for reserving signals for tslots ans extra_params
|
392 |
|
|
-- (Design compiler does not handle empty arrays (e.g. 0 downto -1),
|
393 |
|
|
-- Precision handles them well)
|
394 |
|
|
function max_with_1 (
|
395 |
|
|
constant value : integer) return integer is
|
396 |
|
|
begin -- max_with_1
|
397 |
|
|
if value = 0 then
|
398 |
|
|
return 1;
|
399 |
|
|
else
|
400 |
|
|
return value;
|
401 |
|
|
end if;
|
402 |
|
|
end max_with_1;
|
403 |
|
|
|
404 |
|
|
function log2 (
|
405 |
|
|
constant value : integer) return integer is
|
406 |
|
|
|
407 |
|
|
variable temp : integer := 1;
|
408 |
|
|
variable counter : integer := 0;
|
409 |
|
|
begin -- log2
|
410 |
|
|
temp := 1;
|
411 |
|
|
counter := 0;
|
412 |
|
|
for i in 0 to 31 loop
|
413 |
|
|
if temp < value then
|
414 |
|
|
temp := temp*2;
|
415 |
|
|
counter := counter+1;
|
416 |
|
|
end if;
|
417 |
|
|
end loop;
|
418 |
|
|
|
419 |
|
|
return counter;
|
420 |
|
|
end log2;
|
421 |
|
|
|
422 |
|
|
|
423 |
|
|
-- Calculate the maximum size of configuration
|
424 |
|
|
-- memory page. There are 8 parameters and address,
|
425 |
|
|
-- each time slots requires 3 parameters (start, stop, owner),
|
426 |
|
|
-- and there may be some application specific extra parameters as well.
|
427 |
|
|
|
428 |
|
|
-- E.g. if n_time_slots_g = n_extra_params_g=1
|
429 |
|
|
-- then page_size_c= (8+1)+(1*3)+1= 13 parameters
|
430 |
|
|
constant n_time_slots_tmp_c : integer := max_with_1 (n_time_slots_g);
|
431 |
|
|
constant n_extra_params_tmp_c : integer := max_with_1 (n_extra_params_g);
|
432 |
|
|
|
433 |
|
|
constant page_size_c : integer := 8 + 1 + (n_time_slots_tmp_c * 3)
|
434 |
|
|
+ n_extra_params_tmp_c;
|
435 |
|
|
|
436 |
|
|
constant page_addr_width_c : integer := log2 (page_size_c);
|
437 |
|
|
constant param_addr_width_c : integer := log2 (n_cfg_pages_g) +1;
|
438 |
|
|
constant cfg_addr_width_c : integer := param_addr_width_c
|
439 |
|
|
+ page_addr_width_c;
|
440 |
|
|
|
441 |
|
|
-- These dbg signals can be viewed from Modelsim to check above
|
442 |
|
|
-- calculations manually
|
443 |
|
|
signal pag : integer := page_addr_width_c;
|
444 |
|
|
signal par : integer := param_addr_width_c;
|
445 |
|
|
signal cfg_a : integer := cfg_addr_width_c;
|
446 |
|
|
|
447 |
|
|
|
448 |
|
|
-- Signals (Conf. mem => ) Transmitter => Receiver
|
449 |
|
|
-- signal cfg_rom_en_tx_rx : std_logic;
|
450 |
|
|
-- signal id_tx_rx : std_logic_vector ( id_width_g-1 downto 0);
|
451 |
|
|
-- signal base_id_tx_rx : std_logic_vector ( id_width_g -1 downto 0);
|
452 |
|
|
-- signal base_addr_tx_rx : std_logic_vector ( addr_width_g -1 downto 0);
|
453 |
|
|
|
454 |
|
|
-- Tx-fifo => Tx
|
455 |
|
|
signal av_fifo_tx : std_logic;
|
456 |
|
|
signal data_fifo_tx : std_logic_vector (data_width_g-1 downto 0);
|
457 |
|
|
signal comm_fifo_tx : std_logic_vector (comm_width_g-1 downto 0);
|
458 |
|
|
signal re_tx_fifo : std_logic;
|
459 |
|
|
signal empty_fifo_tx : std_logic;
|
460 |
|
|
signal one_d_fifo_tx : std_logic;
|
461 |
|
|
|
462 |
|
|
-- Rx => Rx-fifo
|
463 |
|
|
signal av_0_rx_fifo : std_logic;
|
464 |
|
|
signal data_0_rx_fifo : std_logic_vector (data_width_g-1 downto 0);
|
465 |
|
|
signal comm_0_rx_fifo : std_logic_vector (comm_width_g-1 downto 0);
|
466 |
|
|
signal we_0_rx_fifo : std_logic;
|
467 |
|
|
signal full_0_fifo_rx : std_logic;
|
468 |
|
|
signal one_0_p_fifo_rx : std_logic;
|
469 |
|
|
|
470 |
|
|
signal av_1_rx_fifo : std_logic;
|
471 |
|
|
signal data_1_rx_fifo : std_logic_vector (data_width_g-1 downto 0);
|
472 |
|
|
signal comm_1_rx_fifo : std_logic_vector (comm_width_g-1 downto 0);
|
473 |
|
|
signal we_1_rx_fifo : std_logic;
|
474 |
|
|
signal full_1_fifo_rx : std_logic;
|
475 |
|
|
signal one_1_p_fifo_rx : std_logic;
|
476 |
|
|
|
477 |
|
|
-- Tx => Rx
|
478 |
|
|
signal cfg_rd_rdy_tx_rx : std_logic;
|
479 |
|
|
|
480 |
|
|
-- Signals Receiver => Transmitter
|
481 |
|
|
signal cfg_addr_rx_tx : std_logic_vector(cfg_addr_width_c -1 downto 0);
|
482 |
|
|
signal cfg_data_rx_tx :
|
483 |
|
|
std_logic_vector (data_width_g-1-(separate_addr_g*addr_width_g) downto 0);
|
484 |
|
|
signal cfg_ret_addr_rx_tx : std_logic_vector(addr_width_g -1 downto 0);
|
485 |
|
|
signal cfg_re_rx_tx : std_logic;
|
486 |
|
|
signal cfg_we_rx_tx : std_logic;
|
487 |
|
|
|
488 |
|
|
|
489 |
|
|
begin -- structural_muxed_tx_fifos
|
490 |
|
|
|
491 |
|
|
--
|
492 |
|
|
-- Transmission from IP to bus
|
493 |
|
|
--
|
494 |
|
|
|
495 |
|
|
tx_unit : transmitter
|
496 |
|
|
-- tx_unit : entity work.transmitter
|
497 |
|
|
generic map(
|
498 |
|
|
data_width_g => data_width_g,
|
499 |
|
|
addr_width_g => addr_width_g,
|
500 |
|
|
comm_width_g => comm_width_g,
|
501 |
|
|
counter_width_g => counter_width_g,
|
502 |
|
|
|
503 |
|
|
id_g => id_g,
|
504 |
|
|
id_width_g => id_width_g,
|
505 |
|
|
|
506 |
|
|
addr_g => addr_g,
|
507 |
|
|
prior_g => prior_g,
|
508 |
|
|
inv_addr_en_g => inv_addr_en_g,
|
509 |
|
|
max_send_g => max_send_g,
|
510 |
|
|
|
511 |
|
|
cfg_addr_width_g => cfg_addr_width_c,
|
512 |
|
|
-- page_addr_width_g => page_addr_width_g,
|
513 |
|
|
-- param_addr_width_g => param_addr_width_g,
|
514 |
|
|
|
515 |
|
|
arb_type_g => arb_type_g,
|
516 |
|
|
n_agents_g => n_agents_g,
|
517 |
|
|
n_cfg_pages_g => n_cfg_pages_g,
|
518 |
|
|
n_time_slots_g => n_time_slots_g,
|
519 |
|
|
keep_slot_g => keep_slot_g,
|
520 |
|
|
n_extra_params_g => n_extra_params_g,
|
521 |
|
|
cfg_re_g => cfg_re_g,
|
522 |
|
|
cfg_we_g => cfg_we_g,
|
523 |
|
|
separate_addr_g => separate_addr_g,
|
524 |
|
|
debug_width_g => debug_width_g
|
525 |
|
|
)
|
526 |
|
|
port map(
|
527 |
|
|
clk => bus_clk,
|
528 |
|
|
rst_n => rst_n,
|
529 |
|
|
|
530 |
|
|
-- from bus
|
531 |
|
|
lock_in => bus_lock_in,
|
532 |
|
|
full_in => bus_full_in,
|
533 |
|
|
|
534 |
|
|
-- from rx
|
535 |
|
|
cfg_data_in => cfg_data_rx_tx,
|
536 |
|
|
cfg_addr_in => cfg_addr_rx_tx,
|
537 |
|
|
cfg_ret_addr_in => cfg_ret_addr_rx_tx,
|
538 |
|
|
cfg_re_in => cfg_re_rx_tx,
|
539 |
|
|
cfg_we_in => cfg_we_rx_tx,
|
540 |
|
|
|
541 |
|
|
-- from fifo
|
542 |
|
|
av_in => av_fifo_tx,
|
543 |
|
|
data_in => data_fifo_tx,
|
544 |
|
|
comm_in => comm_fifo_tx,
|
545 |
|
|
empty_in => empty_fifo_tx,
|
546 |
|
|
one_d_in => one_d_fifo_tx,
|
547 |
|
|
|
548 |
|
|
-- to bus
|
549 |
|
|
data_out => bus_data_out,
|
550 |
|
|
comm_out => bus_comm_out,
|
551 |
|
|
av_out => bus_av_out,
|
552 |
|
|
lock_out => bus_lock_out,
|
553 |
|
|
|
554 |
|
|
-- to rx
|
555 |
|
|
cfg_rd_rdy_out => cfg_rd_rdy_tx_rx,
|
556 |
|
|
--id_out => id_tx_rx,
|
557 |
|
|
--base_id_out => base_id_tx_rx,
|
558 |
|
|
--base_addr_out => base_addr_tx_rx,
|
559 |
|
|
--inv_addr_en_out => cfg_rom_en_tx_rx,
|
560 |
|
|
|
561 |
|
|
-- to fifo
|
562 |
|
|
re_out => re_tx_fifo
|
563 |
|
|
|
564 |
|
|
-- synthesis translate_off
|
565 |
|
|
-- pragma synthesis_off
|
566 |
|
|
-- pragma translate_off
|
567 |
|
|
,
|
568 |
|
|
debug_in => debug_in,
|
569 |
|
|
debug_out => debug_out
|
570 |
|
|
-- pragma translate_on
|
571 |
|
|
-- pragma synthesis_on
|
572 |
|
|
-- synthesis translate_on
|
573 |
|
|
);
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
|
577 |
|
|
|
578 |
|
|
tx_fifo_mux : double_fifo_mux_rd
|
579 |
|
|
generic map(
|
580 |
|
|
fifo_sel_g => fifo_sel_g,
|
581 |
|
|
re_freq_g => rel_bus_freq_g,
|
582 |
|
|
we_freq_g => rel_agent_freq_g,
|
583 |
|
|
depth_0_g => tx_msg_fifo_depth_g,
|
584 |
|
|
depth_1_g => tx_fifo_depth_g,
|
585 |
|
|
data_width_g => data_width_g,
|
586 |
|
|
debug_width_g => 0,
|
587 |
|
|
comm_width_g => comm_width_g,
|
588 |
|
|
separate_addr_g => separate_addr_g
|
589 |
|
|
)
|
590 |
|
|
port map(
|
591 |
|
|
-- re bus side, we agent side
|
592 |
|
|
clk_re => bus_clk,
|
593 |
|
|
clk_we => agent_clk,
|
594 |
|
|
clk_re_pls => bus_sync_clk,
|
595 |
|
|
clk_we_pls => agent_sync_clk,
|
596 |
|
|
rst_n => rst_n,
|
597 |
|
|
|
598 |
|
|
av_0_in => agent_msg_av_in,
|
599 |
|
|
data_0_in => agent_msg_data_in,
|
600 |
|
|
comm_0_in => agent_msg_comm_in,
|
601 |
|
|
we_0_in => agent_msg_we_in,
|
602 |
|
|
one_p_0_out => agent_msg_one_p_out,
|
603 |
|
|
full_0_out => agent_msg_full_out,
|
604 |
|
|
|
605 |
|
|
data_1_in => agent_data_in,
|
606 |
|
|
comm_1_in => agent_comm_in,
|
607 |
|
|
av_1_in => agent_av_in,
|
608 |
|
|
we_1_in => agent_we_in,
|
609 |
|
|
one_p_1_out => agent_one_p_out,
|
610 |
|
|
full_1_out => agent_full_out,
|
611 |
|
|
|
612 |
|
|
re_in => re_tx_fifo,
|
613 |
|
|
data_out => data_fifo_tx,
|
614 |
|
|
comm_out => comm_fifo_tx,
|
615 |
|
|
av_out => av_fifo_tx,
|
616 |
|
|
empty_out => empty_fifo_tx,
|
617 |
|
|
one_d_out => one_d_fifo_tx
|
618 |
|
|
);
|
619 |
|
|
|
620 |
|
|
|
621 |
|
|
--
|
622 |
|
|
-- Reception: from bus to IP
|
623 |
|
|
--
|
624 |
|
|
|
625 |
|
|
rx_unit : receiver
|
626 |
|
|
-- rx_unit : entity work.receiver
|
627 |
|
|
generic map(
|
628 |
|
|
id_g => id_g,
|
629 |
|
|
id_min_g => id_min_g,
|
630 |
|
|
id_max_g => id_max_g,
|
631 |
|
|
id_width_g => id_width_g,
|
632 |
|
|
addr_base_g => addr_g,
|
633 |
|
|
addr_limit_g => addr_limit_g,
|
634 |
|
|
data_width_g => data_width_g,
|
635 |
|
|
addr_width_g => addr_width_g,
|
636 |
|
|
cfg_addr_width_g => cfg_addr_width_c,
|
637 |
|
|
cfg_re_g => cfg_re_g,
|
638 |
|
|
cfg_we_g => cfg_we_g,
|
639 |
|
|
inv_addr_en_g => inv_addr_en_g,
|
640 |
|
|
separate_addr_g => separate_addr_g
|
641 |
|
|
)
|
642 |
|
|
port map(
|
643 |
|
|
clk => bus_clk,
|
644 |
|
|
rst_n => rst_n,
|
645 |
|
|
|
646 |
|
|
av_in => bus_av_in,
|
647 |
|
|
data_in => bus_data_in,
|
648 |
|
|
comm_in => bus_comm_in,
|
649 |
|
|
cfg_rd_rdy_in => cfg_rd_rdy_tx_rx,
|
650 |
|
|
|
651 |
|
|
--id_in => id_tx_rx,
|
652 |
|
|
--base_addr_in => base_addr_tx_rx,
|
653 |
|
|
--inv_addr_en_in => cfg_rom_en_tx_rx,
|
654 |
|
|
|
655 |
|
|
av_0_out => av_0_rx_fifo,
|
656 |
|
|
data_0_out => data_0_rx_fifo,
|
657 |
|
|
comm_0_out => comm_0_rx_fifo,
|
658 |
|
|
we_0_out => we_0_rx_fifo,
|
659 |
|
|
full_0_in => full_0_fifo_rx,
|
660 |
|
|
one_p_0_in => one_0_p_fifo_rx,
|
661 |
|
|
|
662 |
|
|
av_1_out => av_1_rx_fifo,
|
663 |
|
|
data_1_out => data_1_rx_fifo,
|
664 |
|
|
comm_1_out => comm_1_rx_fifo,
|
665 |
|
|
we_1_out => we_1_rx_fifo,
|
666 |
|
|
full_1_in => full_1_fifo_rx,
|
667 |
|
|
one_p_1_in => one_1_p_fifo_rx,
|
668 |
|
|
|
669 |
|
|
bus_full_in => bus_full_in,
|
670 |
|
|
cfg_addr_out => cfg_addr_rx_tx,
|
671 |
|
|
cfg_data_out => cfg_data_rx_tx,
|
672 |
|
|
cfg_ret_addr_out => cfg_ret_addr_rx_tx,
|
673 |
|
|
cfg_we_out => cfg_we_rx_tx,
|
674 |
|
|
cfg_re_out => cfg_re_rx_tx,
|
675 |
|
|
full_out => bus_full_out
|
676 |
|
|
);
|
677 |
|
|
|
678 |
|
|
|
679 |
|
|
|
680 |
|
|
rx_fifo_mux : double_fifo_demux_wr
|
681 |
|
|
generic map(
|
682 |
|
|
fifo_sel_g => fifo_sel_g,
|
683 |
|
|
re_freq_g => rel_agent_freq_g,
|
684 |
|
|
we_freq_g => rel_bus_freq_g,
|
685 |
|
|
depth_0_g => rx_msg_fifo_depth_g,
|
686 |
|
|
depth_1_g => rx_fifo_depth_g,
|
687 |
|
|
data_width_g => data_width_g,
|
688 |
|
|
debug_width_g => 0,
|
689 |
|
|
comm_width_g => comm_width_g
|
690 |
|
|
)
|
691 |
|
|
port map(
|
692 |
|
|
-- re is handled by agent side, we by bus side
|
693 |
|
|
clk_re => agent_clk,
|
694 |
|
|
clk_we => bus_clk,
|
695 |
|
|
clk_re_pls => agent_sync_clk,
|
696 |
|
|
clk_we_pls => bus_sync_clk,
|
697 |
|
|
rst_n => rst_n,
|
698 |
|
|
|
699 |
|
|
av_0_in => av_0_rx_fifo,
|
700 |
|
|
data_0_in => data_0_rx_fifo,
|
701 |
|
|
comm_0_in => comm_0_rx_fifo,
|
702 |
|
|
we_0_in => we_0_rx_fifo,
|
703 |
|
|
full_0_out => full_0_fifo_rx,
|
704 |
|
|
one_p_0_out => one_0_p_fifo_rx,
|
705 |
|
|
|
706 |
|
|
av_1_in => av_1_rx_fifo,
|
707 |
|
|
data_1_in => data_1_rx_fifo,
|
708 |
|
|
comm_1_in => comm_1_rx_fifo,
|
709 |
|
|
we_1_in => we_1_rx_fifo,
|
710 |
|
|
full_1_out => full_1_fifo_rx,
|
711 |
|
|
one_p_1_out => one_1_p_fifo_rx,
|
712 |
|
|
|
713 |
|
|
re_0_in => agent_msg_re_in,
|
714 |
|
|
av_0_out => agent_msg_av_out,
|
715 |
|
|
data_0_out => agent_msg_data_out,
|
716 |
|
|
comm_0_out => agent_msg_comm_out,
|
717 |
|
|
empty_0_out => agent_msg_empty_out,
|
718 |
|
|
one_d_0_out => agent_msg_one_d_out,
|
719 |
|
|
|
720 |
|
|
re_1_in => agent_re_in,
|
721 |
|
|
av_1_out => agent_av_out,
|
722 |
|
|
data_1_out => agent_data_out,
|
723 |
|
|
comm_1_out => agent_comm_out,
|
724 |
|
|
empty_1_out => agent_empty_out,
|
725 |
|
|
one_d_1_out => agent_one_d_out
|
726 |
|
|
);
|
727 |
|
|
|
728 |
|
|
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
|
732 |
|
|
end structural;
|