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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [vhd/] [lfsr.vhd] - Blame information for rev 145

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1 145 lanttu 
---------------------------------------------------------------------
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-- Design unit: lfsr(rtl) (Entity and Architecture)
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--            :
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-- File name  : lfsr.vhd
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--            :
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-- Description: RTL model of LFSR
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--            :
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-- Limitations: None
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--            :
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-- System     : VHDL'93, STD_LOGIC_1164
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--            :
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-- Author     : Mark Zwolinski
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--            : Department of Electronics and Computer Science
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--            : University of Southampton
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--            : Southampton SO17 1BJ, UK
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--            : mz@ecs.soton.ac.uk
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--
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-- Revision   : Version 1.0 08/03/00
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-- 09.05.2007 AK mod: uses 0.5x registers compared to the orig.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity lfsr is
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  generic(
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    width_g : integer range 1 to 36 := 8
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    );
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  port(
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    rst_n     : in  std_logic;
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    enable_in : in  std_logic;
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    q_out     : out std_logic_vector(width_g-1 downto 0);
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    clk       : in  std_logic
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    );
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end entity lfsr;
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architecture rtl of lfsr is
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  type tap_table is array (1 to 36, 1 to 4) of
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    integer range -1 to 36;
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  constant taps : tap_table := (
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    (0, -1, -1, -1),                    -- 1
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    (1, 0, -1, -1),                     -- 2
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    (1, 0, -1, -1),                     -- 3
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    (1, 0, -1, -1),                     -- 4
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    (2, 0, -1, -1),                     -- 5
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    (1, 0, -1, -1),                     -- 6
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    (1, 0, -1, -1),                     -- 7
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    (6, 5, 1, 0),                       -- 8
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    (4, 0, -1, -1),                     -- 9
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    (3, 0, -1, -1),                     --10
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    (2, 0, -1, -1),                     --11
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    (7, 4, 3, 0),                       --12
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    (4, 3, 1, 0),                       --13
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    (12, 11, 1, 0),                     --14
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    (1, 0, -1, -1),                     --15
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    (5, 3, 2, 0),                       --16
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    (3, 0, -1, -1),                     --17
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    (7, 0, -1, -1),                     --18
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    (6, 5, 1, 0),                       --19
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    (3, 0, -1, -1),                     --20
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    (2, 0, -1, -1),                     --21
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    (1, 0, -1, -1),                     --22
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    (5, 0, -1, -1),                     --23
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    (4, 3, 1, 0),                       --24
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    (3, 0, -1, -1),                     --25
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    (8, 7, 1, 0),                       --26
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    (8, 7, 1, 0),                       --27
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    (3, 0, -1, -1),                     --28
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    (2, 0, -1, -1),                     --29
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    (16, 15, 1, 0),                     --30
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    (3, 0, -1, -1),                     --31
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    (28, 27, 1, 0),                     --32
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    (13, 0, -1, -1),                    --33
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    (15, 14, 1, 0),                     --34
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    (2, 0, -1, -1),                     --35
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    (11, 0, -1, -1));                   --36
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  signal ak_test : std_logic_vector(width_g-1 downto 0);
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begin
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  p0 : process (clk, rst_n) is
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    variable reg      : std_logic_vector(width_g-1 downto 0);
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    variable feedback : std_logic;
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  begin
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    if rst_n = '0' then
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      reg     := (others => '1');
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--      q_out   <= (others => '0');
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      ak_test <= (others => '1');
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    elsif  clk'event and clk = '1' then
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      if enable_in = '1' then
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        feedback := ak_test(taps(width_g, 1));
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        for i in 2 to 4 loop
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          if taps(width_g, i) >= 0 then
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            feedback := feedback xor ak_test(taps(width_g, i));
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          end if;
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        end loop;
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        reg     := feedback & reg(width_g-1 downto 1);
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        ak_test <= reg;
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      else
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        ak_test <= ak_test;
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      end if;
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    end if;
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  end process p0;
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    q_out <= ak_test;
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end architecture rtl;
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