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\documentclass[a4paper,10pt,oneside,final]{article}
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stringstyle=\color[rgb]{0.627,0.126,0.941},
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backgroundcolor=\color{white},
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%
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% Define author(s) and component's name
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%
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\def\defauthor{Lasse Lehtonen}
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\def\deftitle{HIBI\_PE\_DMA\\Reference Manual}
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\author{\defauthor}
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\title{\deftitle}
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\usepackage{fancyhdr}
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\pagestyle{fancy}
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\lhead{\bfseries Department of Computer Systems\\
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Faculty of Computing and Electrical Engineering}
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\chead{}
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\rhead{\bfseries \deftitle}
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\lfoot{\thepage}
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\rfoot{\includegraphics[height=1.0cm]{pic/tty_logo.png}}
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\def\deftablecolorb{white}
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\begin{document}
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%\maketitle
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%\thispagestyle{empty}
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\begin{titlepage}
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\begin{center}
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\vspace{6.0cm}
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\textsc{\LARGE Tampere University of Technology}\\[1.0cm]
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\textsc{\Large Faculty of Computing and Electrical Engineering}\\[1.0cm]
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\textsc{\Large Department of Computer Systems}\\[1.0cm]
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\vspace{6.0cm}
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\hrule
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\vspace{0.4cm}
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{ \huge \bfseries HIBI\_PE\_DMA\\\vspace{10pt}HW Reference Manual}
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\vspace{0.4cm}
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\hrule
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%\vspace{2.0cm}
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\vfill
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\begin{minipage}{0.4\textwidth}
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\begin{flushleft} \large
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\emph{Author:}\\
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\defauthor
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\end{flushleft}
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\end{minipage}
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\begin{minipage}{0.4\textwidth}
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\begin{flushright} \large
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\emph{Updated:} \\
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\today
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\end{flushright}
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\end{minipage}
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\end{center}
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\end{titlepage}
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\newpage
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\tableofcontents
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\newpage
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\section{REVISION HISTORY}
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\setcounter{page}{1}
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Revision & Author & Date & Description\\
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\hline
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1.03 & Lasse Lehtonen & 26.01.2012 & Ported old document to Latex\\
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1.04 & Lasse Lehtonen & 27.01.2012 & Added streaming channels\\
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1.05 & Lasse Lehtonen & 02.03.2012 & Removed SW part and changed register order\\
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& & & \\
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& & & \\
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\hline
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\end{tabularx}
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\end{center}
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\newpage
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\section{DOCUMENT OVERVIEW}
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\subsection{SCOPE}
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This documentation describes how to use HIBI PE DMA component.
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\subsection{AUDIENCE}
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For hardware integrators and software developers using this component.
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\subsection{RELATED DOCUMENTATION}
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\begin{center}
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\rowcolors[]{2}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lX|}
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\hline
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Document & Description\\
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\hline
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building\_test\_system.pptx & Descibes an example using in SOPC
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with NIOS II processors\\
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hpd\_sw\_ref.pdf & Software reference manual\\
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HIBI\_PE\_DMA.pptx & Introduction to HIBI PE DMA\\
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\hline
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\end{tabularx}
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\end{center}
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\subsection{DOCUMENT CONVENTIONS}
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\begin{itemize}
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\item Ports: \texttt{teletype} in text
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\item Generics: \texttt{teletype} in text
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\end{itemize}
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\newpage
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\section{INTRODUCTION}
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\subsection{BRIEF DESCRIPTION}
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HIBI\_PE\_DMA (HPD) component allows separate processor systems with
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Avalon-MM compatible interface to communicate with each other via Hibi
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hierarchical bus. Communication is DMA based and uses either packet or
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stream channels for network transactions. HIBI\_PE\_DMA supports both
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polling and interrupts.
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\subsection{EXAMPLE SYSTEM}
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Example system showing three SOPC blocks with Nios processors
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communicating via Hibi. Each HIBI\_PE\_DMA component is associated
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with dual-port RAMs where they store received data and read the data
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to be sent.
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\begin{center}
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\includegraphics[width=0.8\textwidth]{pic/example_system.png}
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\captionof{figure}{Example system with three Nios processors}
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\label{fig:example_system}
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\end{center}
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\newpage
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\section{HARDWARE DESIGN}
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\subsection{HIBI\_PE\_DMA}
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\subsubsection{GENERICS}
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lX|}
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\hline
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Name & Description\\
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\hline
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data\_width\_g & Width of the data buses\\
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addr\_width\_g & Width of the Hibi address\\
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words\_width\_g & Number of bits needed to represent word counters\\
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n\_stream\_chans\_g & Number of stream channels\\
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n\_packet\_chans\_g & Number of packet channels\\
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n\_chans\_bits\_g & Bits needed to represent n\_stream\_chans\_g +
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n\_packet\_chans\_g\\
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hibi\_addr\_cmp\_lo\_g & Lower boundary for address comparison\\
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hibi\_addr\_cmp\_hi\_g & Upper boundary for address comparison\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{CLOCKING AND RESET}
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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clk & 1 & in & Clock, active on rising edge\\
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rst\_n & 1 & in & Reset, asynchronous, active low\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{CONFIGURATION INTERFACE}
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This slave interface is used by the processor for reading or writing
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HIBI\_PE\_DMA registers.
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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avalon\_cfg\_addr\_in & n\_chans\_g+4 & in & Register address\\
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avalon\_cfg\_writedata\_in & addr\_width\_g & in & Data in\\
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avalon\_cfg\_we\_in & 1 & in & Write enable\\
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avalon\_cfg\_readdata\_out & addr\_width\_g & out & Data out\\
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avalon\_cfg\_re\_in & 1 & in & Read enable\\
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avalon\_cfg\_cs\_in & 1 & in & Chip select\\
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avalon\_cfg\_waitrequest\_out & 1 & out & Stall\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{MEMORY WRITE INTERFACE}
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This master interface is used by HIBI\_PE\_DMA to write received data to the
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shared dual-port memory.
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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avalon\_addr\_out\_rx & addr\_width\_g & out & Write address\\
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avalon\_we\_out\_rx & 1 & out & Write enable\\
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avalon\_be\_out\_rx & data\_width\_g / 8 & out & Byte enable\\
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avalon\_writedata\_out\_rx & data\_width\_g & out & Data out\\
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avalon\_waitrequest\_in\_rx & 1 & in & Stall\\
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\hline
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\end{tabularx}
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\end{center}
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\pagebreak
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\subsubsection{MEMORY READ INTERFACE}
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This master interface is used by HIBI\_PE\_DMA to read data to be sent from the
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shared dual-port memory.
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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avalon\_addr\_out\_tx & addr\_width\_g & out & Read address\\
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avalon\_re\_out\_tx & 1 & out & Read enable\\
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avalon\_readdata\_in\_tx & data\_width\_g & in & Data in\\
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avalon\_waitrequest\_in\_tx & 1 & in & Stall\\
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avalon\_readdatavalid\_in\_tx & 1 & out & Byte enable\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{HIBI RECEIVE INTERFACE}
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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hibi\_data\_in & data\_width\_g & in & Data in\\
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hibi\_av\_in & 1 & in & Address valid\\
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hibi\_empty\_in & 1 & in & No more data\\
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hibi\_comm\_in & 5 & in & Hibi command\\
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hibi\_re\_out & 1 & out & Read enable\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{HIBI TRANSMIT INTERFACE}
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\begin{center}
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\rowcolors{3}{\deftablecolora}{\deftablecolorb}
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\captionof{table}{}
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\begin{tabularx}{\textwidth}{|lllX|}
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\hline
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Port & Width & Direction & Description\\
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\hline
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hibi\_data\_out & data\_width\_g & in & Data out\\
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hibi\_av\_out & 1 & in & Address valid\\
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hibi\_full\_in & 1 & in & Receiver fulll\\
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hibi\_comm\_out & 5 & in & Hibi command\\
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hibi\_we\_out & 1 & out & Write enable\\
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\hline
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\end{tabularx}
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\end{center}
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\subsubsection{INTERRUPT INTERFACE}
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|
\begin{center}
|
| 359 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 360 |
|
|
|
| 361 |
|
|
\captionof{table}{}
|
| 362 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 363 |
|
|
\hline
|
| 364 |
|
|
Port & Width & Direction & Description\\
|
| 365 |
|
|
\hline
|
| 366 |
|
|
rx\_irq\_out & 1 & out & Interrupt, active high\\
|
| 367 |
|
|
\hline
|
| 368 |
|
|
\end{tabularx}
|
| 369 |
|
|
\end{center}
|
| 370 |
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|
| 371 |
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|
| 372 |
|
|
\pagebreak
|
| 373 |
|
|
\subsubsection{INTERFACE STRUCTURE}
|
| 374 |
|
|
|
| 375 |
|
|
Figure \ref{fig:arch} shows how HIBI\_PE\_DMA's interfaces are connected.
|
| 376 |
|
|
|
| 377 |
|
|
\begin{center}
|
| 378 |
|
|
\includegraphics[width=0.8\textwidth]{pic/arch.png}
|
| 379 |
|
|
\captionof{figure}{HIBI\_PE\_DMA connected to a Processing Element
|
| 380 |
|
|
(PE), dual-port memory and Hibi}
|
| 381 |
|
|
\label{fig:arch}
|
| 382 |
|
|
\end{center}
|
| 383 |
|
|
|
| 384 |
|
|
|
| 385 |
|
|
\subsubsection{INTEGRATION}
|
| 386 |
|
|
|
| 387 |
|
|
Related source files are listed in next table in the order of
|
| 388 |
|
|
compilation (when applicable).
|
| 389 |
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|
|
| 390 |
|
|
\begin{center}
|
| 391 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 392 |
|
|
|
| 393 |
|
|
\captionof{table}{}
|
| 394 |
|
|
\begin{tabularx}{\textwidth}{|lX|}
|
| 395 |
|
|
\hline
|
| 396 |
|
|
Filename & Description\\
|
| 397 |
|
|
\hline
|
| 398 |
|
|
hpd\_tx\_control.vhd & Sending logic\\
|
| 399 |
|
|
hpd\_rx\_packet.vhd & RX packet channel\\
|
| 400 |
|
|
hpd\_rx\_stream.vhd & RX stream channel\\
|
| 401 |
|
|
hpd\_rx\_and\_conf.vhd & RX channels and configuration registers\\
|
| 402 |
|
|
hibi\_pe\_dma.vhd & Top level\\
|
| 403 |
|
|
\hline
|
| 404 |
|
|
\end{tabularx}
|
| 405 |
|
|
\end{center}
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
\pagebreak
|
| 409 |
|
|
\subsubsection{REGISTERS}
|
| 410 |
|
|
|
| 411 |
|
|
\begin{center}
|
| 412 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 413 |
|
|
|
| 414 |
|
|
\captionof{table}{}
|
| 415 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 416 |
|
|
\hline
|
| 417 |
|
|
Address & Name & Access & Description\\
|
| 418 |
|
|
\hline
|
| 419 |
|
|
0x00 & RX\_INITIALIZE & W & Initializes channels\\
|
| 420 |
|
|
0x01 & CONTROL & RW & Control register\\
|
| 421 |
|
|
0x02 & IRQ\_STATUS & RW & Read IRQ status and acknowledge interrupts\\
|
| 422 |
|
|
0x03 & TX\_MEM\_ADDR & W & Address where data to be sent begins\\
|
| 423 |
|
|
0x04 & TX\_WORDS & W & How many words to send\\
|
| 424 |
|
|
0x05 & TX\_COMM & W & Hibi command to send the data with\\
|
| 425 |
|
|
0x06 & TX\_HIBI\_ADDR & W & Hibi address to send the data\\
|
| 426 |
|
|
0x07 & RX\_HIBI\_DATA & R & Current data on hibi rx interface\\
|
| 427 |
|
|
0xn8 & RX\_MEM\_ADDR & RW & Address where channel n stores received data\\
|
| 428 |
|
|
0xn9 & RX\_WORDS & RW & How many words to receive for packet channel n
|
| 429 |
|
|
or read acknowledge for stream channel n\\
|
| 430 |
|
|
0xnA & RX\_HIBI\_ADDR & RW & Hibi address for channel n to listen\\
|
| 431 |
|
|
\hline
|
| 432 |
|
|
\end{tabularx}
|
| 433 |
|
|
\end{center}
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
\paragraph{RX\_INITIALIZE REGISTER (0x00)} initializes channels with
|
| 437 |
|
|
previously set data. For every bit that is '1' corresponding channel
|
| 438 |
|
|
is initializes. Eg. if bit 3 is '1' then channel 3 will be
|
| 439 |
|
|
initialized. Initialization means that the channel reads in registers
|
| 440 |
|
|
0xn0-0xn3 and starts listening hibi receive interface.
|
| 441 |
|
|
|
| 442 |
|
|
\begin{center}
|
| 443 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 444 |
|
|
|
| 445 |
|
|
\captionof{table}{}
|
| 446 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 447 |
|
|
\hline
|
| 448 |
|
|
Bit & Name & Access & Description\\
|
| 449 |
|
|
\hline
|
| 450 |
|
|
[total\_channels-1:0] & INIT & W & Initialize channels\\
|
| 451 |
|
|
\hline
|
| 452 |
|
|
\end{tabularx}
|
| 453 |
|
|
\end{center}
|
| 454 |
|
|
|
| 455 |
|
|
|
| 456 |
|
|
\paragraph{CONTROL REGISTER (0x01)} is used to enable interrupts,
|
| 457 |
|
|
start sending and checking if transmission has been done.
|
| 458 |
|
|
|
| 459 |
|
|
\begin{center}
|
| 460 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 461 |
|
|
|
| 462 |
|
|
\captionof{table}{}
|
| 463 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 464 |
|
|
\hline
|
| 465 |
|
|
Bit & Name & Access & Description\\
|
| 466 |
|
|
\hline
|
| 467 |
|
|
|
| 468 |
|
|
1 & IE & RW & Interrupt enable\\
|
| 469 |
|
|
16 & TXDONE & R & Transmission completed\\
|
| 470 |
|
|
\hline
|
| 471 |
|
|
\end{tabularx}
|
| 472 |
|
|
\end{center}
|
| 473 |
|
|
|
| 474 |
|
|
|
| 475 |
|
|
\paragraph{IRQ\_STATUS REGISTER (0x02)} holds the interrupt status.
|
| 476 |
|
|
Channel interrupts are acknowledged by writing '1' to the
|
| 477 |
|
|
corresponding bit, other interrupt goes low automatically when this
|
| 478 |
|
|
register is read. IGNORED\_TX is '1' if transmission was tried when
|
| 479 |
|
|
previous transmission was still going on. UNKNOWN\_RX is '1' when
|
| 480 |
|
|
hibi\_data\_in line has an address that isn't listened by any channel.
|
| 481 |
|
|
|
| 482 |
|
|
\begin{center}
|
| 483 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 484 |
|
|
|
| 485 |
|
|
\captionof{table}{}
|
| 486 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 487 |
|
|
\hline
|
| 488 |
|
|
Bit & Name & Access & Description\\
|
| 489 |
|
|
\hline
|
| 490 |
|
|
[total\_channels-1:0] & IRQ & RW & Channel interrupt statuses\\
|
| 491 |
|
|
addr\_width\_g-2 & IGNORED\_TX & R & Last transmission ignored\\
|
| 492 |
|
|
addr\_width\_g-1 & UNKOWN\_RX & R & Received unknown hibi address\\
|
| 493 |
|
|
\hline
|
| 494 |
|
|
\end{tabularx}
|
| 495 |
|
|
\end{center}
|
| 496 |
|
|
|
| 497 |
|
|
|
| 498 |
|
|
\paragraph{TX\_MEM\_ADDR REGISTER (0x03)} tells HIBI\_PE\_DMA where
|
| 499 |
|
|
the beginning of the packet to be sent is in the shared memory.
|
| 500 |
|
|
|
| 501 |
|
|
\begin{center}
|
| 502 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 503 |
|
|
|
| 504 |
|
|
\captionof{table}{}
|
| 505 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 506 |
|
|
\hline
|
| 507 |
|
|
Bit & Name & Access & Description\\
|
| 508 |
|
|
\hline
|
| 509 |
|
|
[addr\_width\_g-1:0] & ADDRESS & W & Packet's starting address\\
|
| 510 |
|
|
\hline
|
| 511 |
|
|
\end{tabularx}
|
| 512 |
|
|
\end{center}
|
| 513 |
|
|
|
| 514 |
|
|
|
| 515 |
|
|
\paragraph{TX\_WORDS REGISTER (0x04)} defines the amount of words
|
| 516 |
|
|
to send.
|
| 517 |
|
|
|
| 518 |
|
|
|
| 519 |
|
|
\begin{center}
|
| 520 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 521 |
|
|
|
| 522 |
|
|
\captionof{table}{}
|
| 523 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 524 |
|
|
\hline
|
| 525 |
|
|
Bit & Name & Access & Description\\
|
| 526 |
|
|
\hline
|
| 527 |
|
|
[words\_width\_g-1:0] & WORDS & W & How many words to send\\
|
| 528 |
|
|
\hline
|
| 529 |
|
|
\end{tabularx}
|
| 530 |
|
|
\end{center}
|
| 531 |
|
|
|
| 532 |
|
|
|
| 533 |
|
|
\paragraph{TX\_COMM REGISTER (0x05)} defines witch hibi command to
|
| 534 |
|
|
use when sending the data.
|
| 535 |
|
|
|
| 536 |
|
|
\begin{center}
|
| 537 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 538 |
|
|
|
| 539 |
|
|
\captionof{table}{}
|
| 540 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 541 |
|
|
\hline
|
| 542 |
|
|
Bit & Name & Access & Description\\
|
| 543 |
|
|
\hline
|
| 544 |
|
|
[4:0] & CMD & W & Hibi command\\
|
| 545 |
|
|
\hline
|
| 546 |
|
|
\end{tabularx}
|
| 547 |
|
|
\end{center}
|
| 548 |
|
|
|
| 549 |
|
|
|
| 550 |
|
|
\paragraph{TX\_HIBI\_ADDR REGISTER (0x06)} is used as the target
|
| 551 |
|
|
hibi address when sending.
|
| 552 |
|
|
|
| 553 |
|
|
|
| 554 |
|
|
\begin{center}
|
| 555 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 556 |
|
|
|
| 557 |
|
|
\captionof{table}{}
|
| 558 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 559 |
|
|
\hline
|
| 560 |
|
|
Bit & Name & Access & Description\\
|
| 561 |
|
|
\hline
|
| 562 |
|
|
[addr\_width\_g-1:0] & ADDR & W & Hibi address to use\\
|
| 563 |
|
|
\hline
|
| 564 |
|
|
\end{tabularx}
|
| 565 |
|
|
\end{center}
|
| 566 |
|
|
|
| 567 |
|
|
|
| 568 |
|
|
\paragraph{RX\_HIBI\_DATA REGISTER (0x07)} is used to read
|
| 569 |
|
|
the unknown incoming address from hibi. When HIBI\_PE\_DMA receives an
|
| 570 |
|
|
address from hibi bus that no channel is listening it stalls the hibi
|
| 571 |
|
|
and raises an interrupt. This register can then be used to read the
|
| 572 |
|
|
address.
|
| 573 |
|
|
|
| 574 |
|
|
\begin{center}
|
| 575 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 576 |
|
|
|
| 577 |
|
|
\captionof{table}{}
|
| 578 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 579 |
|
|
\hline
|
| 580 |
|
|
Bit & Name & Access & Description\\
|
| 581 |
|
|
\hline
|
| 582 |
|
|
[addr\_width\_g-1:0] & ADDR & R & Contents of hibi\_data\_in bus\\
|
| 583 |
|
|
\hline
|
| 584 |
|
|
\end{tabularx}
|
| 585 |
|
|
\end{center}
|
| 586 |
|
|
|
| 587 |
|
|
|
| 588 |
|
|
\paragraph{RX\_MEM\_ADDR REGISTER (0xn8)} holds the address of the
|
| 589 |
|
|
beginning of the memory area where to store incoming data from channel
|
| 590 |
|
|
n. Area should be at least as big as the amount of words to receive
|
| 591 |
|
|
specified with register 0xn2. Address is updated only when channel is
|
| 592 |
|
|
initialized.
|
| 593 |
|
|
|
| 594 |
|
|
\begin{center}
|
| 595 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 596 |
|
|
|
| 597 |
|
|
\captionof{table}{}
|
| 598 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 599 |
|
|
\hline
|
| 600 |
|
|
Bit & Name & Access & Description\\
|
| 601 |
|
|
\hline
|
| 602 |
|
|
[addr\_width\_g-1:0] & ADDRESS & RW & Where to store data\\
|
| 603 |
|
|
\hline
|
| 604 |
|
|
\end{tabularx}
|
| 605 |
|
|
\end{center}
|
| 606 |
|
|
|
| 607 |
|
|
|
| 608 |
|
|
\paragraph{RX\_WORDS REGISTER (0xn9)} tells packet channels how many
|
| 609 |
|
|
words to receive before interrupting. Amount is updated only when
|
| 610 |
|
|
channel is initialized. For stream channels this register tells the
|
| 611 |
|
|
length of the rx memory region when initialized and for already
|
| 612 |
|
|
initialized stream channels this register acknowledges that WORDS
|
| 613 |
|
|
words have been read from the rx memory and allows the channel to
|
| 614 |
|
|
continue receiving. When read for returns amount of words already
|
| 615 |
|
|
received.
|
| 616 |
|
|
|
| 617 |
|
|
|
| 618 |
|
|
\begin{center}
|
| 619 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 620 |
|
|
|
| 621 |
|
|
\captionof{table}{}
|
| 622 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 623 |
|
|
\hline
|
| 624 |
|
|
Bit & Name & Access & Description\\
|
| 625 |
|
|
\hline
|
| 626 |
|
|
[words\_width\_g-1:0] & WORDS & RW & Words to receive or acknowledge\\
|
| 627 |
|
|
\hline
|
| 628 |
|
|
\end{tabularx}
|
| 629 |
|
|
\end{center}
|
| 630 |
|
|
|
| 631 |
|
|
|
| 632 |
|
|
\paragraph{RX\_HIBI\_ADDR REGISTER (0xnA)} specifies the hibi address
|
| 633 |
|
|
to listen and receive data from. Address is updated only when channel
|
| 634 |
|
|
is initialized.
|
| 635 |
|
|
|
| 636 |
|
|
\begin{center}
|
| 637 |
|
|
\rowcolors{3}{\deftablecolora}{\deftablecolorb}
|
| 638 |
|
|
|
| 639 |
|
|
\captionof{table}{}
|
| 640 |
|
|
\begin{tabularx}{\textwidth}{|lllX|}
|
| 641 |
|
|
\hline
|
| 642 |
|
|
Bit & Name & Access & Description\\
|
| 643 |
|
|
\hline
|
| 644 |
|
|
[addr\_width\_g-1:0] & ADDRESS & RW & Hibi address to listen\\
|
| 645 |
|
|
\hline
|
| 646 |
|
|
\end{tabularx}
|
| 647 |
|
|
\end{center}
|
| 648 |
|
|
|
| 649 |
|
|
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
|
| 653 |
|
|
|
| 654 |
|
|
|
| 655 |
|
|
|
| 656 |
|
|
\end{document}
|
