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lanttu |
-------------------------------------------------------------------------------
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-- Title : Avalon cfg writer
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-- Project :
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-------------------------------------------------------------------------------
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-- File : avalon_cfg_writer.vhd
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-- Author : kulmala3
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-- Created : 22.03.2005
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-- Last update: 2011-11-10
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-- Description: Testbench block to config the dma via avalon.
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-- Gets the needed values from an ASCII file.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2005
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 22.03.2005 1.0 AK Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This file is part of HIBI
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use std.textio.all;
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use work.txt_util.all;
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--use work.log2_pkg.all;
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use work.tb_n2h2_pkg.all;
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entity avalon_cfg_writer is
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generic (
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n_chans_g : integer := 0;
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data_width_g : integer := 0;
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conf_file_g : string := ""
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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start_in : in std_logic;
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avalon_cfg_addr_out : out std_logic_vector(log2(n_chans_g)+conf_bits_c-1 downto 0);
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avalon_cfg_writedata_out : out std_logic_vector(data_width_g-1 downto 0);
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avalon_cfg_we_out : out std_logic;
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avalon_cfg_cs_out : out std_logic;
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init_in : in std_logic;
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done_out : out std_logic
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);
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end avalon_cfg_writer;
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architecture rtl of avalon_cfg_writer is
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signal state_r : integer;
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signal init_state_r : integer;
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signal chan_counter_r : integer;
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begin -- rtl
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--
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-- Simple state machine, states are just numbered 0,1,2...8
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-- Separate part for init on the bottom
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--
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process (clk, rst_n)
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file conf_file : text open read_mode is conf_file_g;
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variable mem_addr_r : integer;
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variable sender_r : integer;
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variable irq_amount_r : integer;
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variable max_amount_r : integer;
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begin -- process
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if rst_n = '0' then -- asynchronous reset (active low)
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chan_counter_r <= 0;
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avalon_cfg_cs_out <= '0';
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avalon_cfg_we_out <= '0';
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avalon_cfg_writedata_out <= (others => '0');
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avalon_cfg_addr_out <= (others => '0');
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done_out <= '0';
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state_r <= 0;
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init_state_r <= 0;
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elsif clk'event and clk = '1' then -- rising clock edge
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case state_r is
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when 0 =>
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if start_in = '1' then
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state_r <= 1;
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done_out <= '0';
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else
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done_out <= '0';
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state_r <= 0;
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end if;
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when 1 =>
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-- Read file and configure mem addr
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read_conf_file (
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mem_addr => mem_addr_r ,
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dst_addr => sender_r,
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irq_amount => irq_amount_r,
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-- max_amount => max_amount_r,
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file_txt => conf_file
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);
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assert false report "mem_addr: " & str(mem_addr_r) severity note;
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assert false report "dst_addr: " & str(sender_r) severity note;
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assert false report "irq_amount: " & str(irq_amount_r) severity note;
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-- assert false report "max_amount_r: " & str(max_amount_r) severity note;
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avalon_cfg_writedata_out <= conv_std_logic_vector(mem_addr_r, data_width_g);
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(0, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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state_r <= 2;
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when 2 =>
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-- Configure noc_addr_r (originally called "sender_r")
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avalon_cfg_writedata_out <= conv_std_logic_vector(sender_r, data_width_g);
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(1, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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state_r <= 3;
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when 3 =>
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-- Confgure expexted word count
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avalon_cfg_writedata_out <= conv_std_logic_vector(irq_amount_r, data_width_g);
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(2, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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state_r <= 5;
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-- obsolete
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-- when 4 =>
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-- avalon_cfg_writedata_out <= conv_std_logic_vector(max_amount_r, data_width_g);
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-- avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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-- conv_std_logic_vector(0, conf_bits_c);
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-- avalon_cfg_we_out <= '1';
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-- avalon_cfg_cs_out <= '1';
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-- state_r <= 5;
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when 5 =>
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-- Set init bit
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avalon_cfg_writedata_out <= (others => '0');
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avalon_cfg_writedata_out(chan_counter_r) <= '1';
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(5, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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state_r <= 6;
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when 6 =>
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-- Set irq_ena bit
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avalon_cfg_writedata_out <= (others => '0');
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avalon_cfg_writedata_out(1) <= '1';
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(4, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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state_r <= 7;
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-- obsolete
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-- when 6 =>
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-- -- reset init
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-- avalon_cfg_writedata_out <= conv_std_logic_vector(2, data_width_g);
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-- avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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-- conv_std_logic_vector(0, conf_bits_c);
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-- avalon_cfg_we_out <= '1';
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-- avalon_cfg_cs_out <= '1';
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-- state_r <= 7;
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when 7 =>
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-- Go to next channel
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avalon_cfg_cs_out <= '0';
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chan_counter_r <= chan_counter_r+1;
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state_r <= 8;
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when 8 =>
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-- Configure next channel or start over
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if chan_counter_r = n_chans_g then
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state_r <= 0;
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chan_counter_r <= 0;
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avalon_cfg_we_out <= '0';
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done_out <= '1';
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else
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state_r <= 1;
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end if;
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when others => null;
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end case;
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if init_in = '1' then
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init_state_r <= 1;
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end if;
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case init_state_r is
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when 1 =>
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-- set init bit
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avalon_cfg_writedata_out <= (others => '0');
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avalon_cfg_writedata_out(chan_counter_r) <= '1';
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avalon_cfg_addr_out <= conv_std_logic_vector(chan_counter_r, log2(n_chans_g)) &
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conv_std_logic_vector(5, conf_bits_c);
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avalon_cfg_we_out <= '1';
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avalon_cfg_cs_out <= '1';
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init_state_r <= 2;
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chan_counter_r <= chan_counter_r+1;
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when 2 =>
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if chan_counter_r = n_chans_g then
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init_state_r <= 0;
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avalon_cfg_we_out <= '0';
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avalon_cfg_cs_out <= '0';
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done_out <= '1';
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chan_counter_r <= 0;
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else
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avalon_cfg_we_out <= '0';
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init_state_r <= 1;
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end if;
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when others => null;
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end case;
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end if;
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end process;
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end rtl;
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