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lanttu |
------------------------------------------------------------
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-- Project : Engine
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-- Author : Ari Kulmala
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-- e-mail : ari.kulmala@tut.fi
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-- Date : 7.7.2004
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-- File : tb_n2h_tx.vhdl
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-- Design : Syncronous testbench for Nios-to-Hibi v2 (N2H2 )transmitter
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-- Unlike rx tb, this does not use config file, but
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-- all the tests are hard-coded into this file.
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------------------------------------------------------------
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-- $Log$
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-- Revision 1.1 2005/04/14 06:45:55 kulmala3
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-- First version to CVS
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--
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-- 31.08.04 AK Streaming
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-- 05.01.04 AK Interface signals naming changed.
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------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This file is part of HIBI
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use work.txt_util.all;
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entity tb_n2h2_tx is
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end tb_n2h2_tx;
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architecture rtl of tb_n2h2_tx is
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constant PERIOD : time := 50 ns;
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constant data_width_c : integer := 32; -- bits
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constant amount_width_c : integer := 9; -- at max 2^amount words sent
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constant addr_width_c : integer := 32; -- bits
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constant addr_offset_c : integer := (data_width_c)/8;
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constant comm_write_c : std_logic_vector(4 downto 0) := "00010";
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constant comm_idle_c : std_logic_vector(4 downto 0) := "00000";
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constant comm_write_msg_c : std_logic_vector(4 downto 0) := "00011";
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constant data_start_c : integer := 0;
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constant wait_req_freq_c : integer := 10;
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-- Clk and reset
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signal clk : std_logic;
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signal clk2 : std_logic;
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signal rst_n : std_logic;
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-- Two-level FSM in the testbench
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-- There are multiple test cases, and each has 4 phases
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type test_states is (test1, test2, test3, stop_tests);
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type test_case_states is (assign, trigger, monitor, finish);
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signal test_ctrl_r : test_states := test1;
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signal test_case_ctrl_r : test_case_states := trigger;
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-- signals from n2h_tx
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signal tx_status_duv_tb : std_logic := '0';
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signal tx_busy_duv_tb : std_logic;
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-- signals from tb to n2h_tx
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signal internal_wait_tb_duv : std_logic := '0';
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signal tx_irq_tb_duv : std_logic;
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signal amount_tb_duv : integer := 0;
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signal amount_vec_tb_duv : std_logic_vector(amount_width_c-1 downto 0);
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signal dpram_vec_addr_tb_duv : std_logic_vector(addr_width_c-1 downto 0);
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signal dpram_addr_tb_duv : integer := 0;
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signal hibi_addr_tb_duv : std_logic_vector (data_width_c-1 downto 0); -- 2011-11-11
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signal comm_tb_duv : std_logic_vector(4 downto 0);
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--Duv=tx writes to hibi with these
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signal hibi_av_duv_tb : std_logic := '0';
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signal hibi_data_duv_tb : integer := 0;
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signal hibi_data_vec_duv_tb : std_logic_vector(data_width_c-1 downto 0);
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signal hibi_comm_duv_tb : std_logic_vector(4 downto 0);
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signal hibi_we_duv_tb : std_logic;
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signal hibi_full_tb_duv : std_logic := '1';
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-- Duv=tx reads meemory via these avalon signals
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signal avalon_addr_duv_tb : std_logic_vector(addr_width_c-1 downto 0);
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signal avalon_read_duv_tb : std_logic;
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signal avalon_vec_readdata_tb_duv : std_logic_vector(data_width_c-1 downto 0);
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signal avalon_readdata_tb_duv : integer := 0;
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signal avalon_waitrequest_tb_duv : std_logic;
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signal avalon_readdatavalid_tb_duv : std_logic;
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-- others
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signal counter_r : integer := 0; -- temp counter_r, no special func
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signal new_hibi_addr_r : integer := 0;
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signal new_amount_r : integer := 0;
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signal new_dpram_addr_r : integer := 0;
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-- which address hibi should get next
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signal global_hibi_addr_r : integer := 0;
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-- global number of data in next packet
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signal global_amount_r : integer := 0;
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signal global_comm_r : std_logic_vector(4 downto 0);
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signal global_dpram_addr : integer := 0; -- given dpram addr
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-- check avalon signals
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signal avalon_data_counter_r : integer := data_start_c; -- data sent
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signal avalon_addr_counter_r : integer := 0; -- avalon addr right?
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signal avalon_amount : integer := 0; -- how many data
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signal avalon_addr_sent : std_logic := '0'; -- if already gave address
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signal avalon_last_addr : integer := 0; -- store the old addr
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-- signal avalon_gave_data : std_logic := 0; -- avalon timing
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-- signal avalon_ok : std_logic := '0'; -- all the avalon data ok
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-- check hibi signals
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signal hibi_addr_came : std_logic; --:= '0';
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signal hibi_data_counter_r : integer := data_start_c; -- data received
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signal hibi_addr : integer := 0; -- right hibi addr
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signal hibi_amount : integer := 0; -- how many datas hibi has received
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-- signal hibi_ok : std_logic := '0'; --hibi received all ok.
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begin -- rtl
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--
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-- Instantiate DUV. Note that this is just one sbu-block
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-- from N2H.
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--
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--
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n2h2_tx_1 : entity work.hpd_tx_control
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generic map (
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data_width_g => data_width_c,
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amount_width_g => amount_width_c
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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-- Avalon master read interface to access the memory
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avalon_addr_out => avalon_addr_duv_tb,
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avalon_readdata_in => avalon_vec_readdata_tb_duv,
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avalon_re_out => avalon_read_duv_tb,
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avalon_waitrequest_in => avalon_waitrequest_tb_duv,
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avalon_readdatavalid_in => avalon_readdatavalid_tb_duv, -- ES 2010/05/07
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-- Hibi interface for sending data
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hibi_data_out => hibi_data_vec_duv_tb,
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hibi_av_out => hibi_av_duv_tb,
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hibi_full_in => hibi_full_tb_duv,
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hibi_comm_out => hibi_comm_duv_tb,
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hibi_we_out => hibi_we_duv_tb,
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-- DMA configuration interface, driven by "N2H ctrl logic" (=tb here)
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tx_start_in => tx_irq_tb_duv,
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tx_status_done_out => tx_status_duv_tb,
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tx_comm_in => comm_tb_duv,
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tx_hibi_addr_in => hibi_addr_tb_duv, --(others => '0'),
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tx_ram_addr_in => dpram_vec_addr_tb_duv,
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tx_amount_in => amount_vec_tb_duv
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);
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-- Processes check_avalon and check_hibi continuously monitor avalon and hibi
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-- buses and automatically check whether the data came right.
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-- It's simple because the sent data is implemented
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-- as a counter and hence the incoming data should be in order.
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-- If theres too much data read from avalon, hibi gets wrong packets
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-- and informs.
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-- If theres too much/few data sent to hibi, hibi informs also.
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-- TB uses integers. Convert them to/from bit vectors for port mapping
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hibi_data_duv_tb <= to_integer(unsigned(hibi_data_vec_duv_tb));
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amount_vec_tb_duv <= std_logic_vector(to_unsigned(amount_tb_duv, amount_width_c));
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dpram_vec_addr_tb_duv <=
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std_logic_vector(to_unsigned(dpram_addr_tb_duv, addr_width_c));
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avalon_vec_readdata_tb_duv <=
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std_logic_vector(to_unsigned(avalon_readdata_tb_duv, data_width_c))
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when avalon_readdatavalid_tb_duv = '1' else (others => 'Z');
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hibi_addr_tb_duv <= std_logic_vector (to_unsigned(global_hibi_addr_r, data_width_c));
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--
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-- "Test" is the main process that is implented as a state machine
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-- (test1, test2 ... etc) so that new tests can be easily implemented
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--
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test : process (clk, rst_n)
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begin -- process test
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if rst_n = '0' then -- asynchronous reset (active low)
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test_ctrl_r <= test1; -- test2;
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test_case_ctrl_r <= trigger; --assign;
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-- Initializations added 2011-11-11, ES
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comm_tb_duv <= comm_idle_c;
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global_comm_r <= comm_idle_c;
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tx_irq_tb_duv <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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case test_ctrl_r is
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-----------------------------------------------------------------------
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-- tests are controlled by following signals, which must be set
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-- global_hibi_addr_r = where to send
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-- global_amount_r = how much to send
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-- global_comm_r = which command to use
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-----------------------------------------------------------------------
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when test1 =>
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-- Basic test: tests action under hibi_full signal
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-- and how one packet is transferred.
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case test_case_ctrl_r is
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when trigger =>
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-- assign and trigger irq.
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if tx_status_duv_tb = '1' then
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global_amount_r <= 1; --4;
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amount_tb_duv <= 1; --4;
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global_hibi_addr_r <= 230;
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global_comm_r <= comm_write_c;
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comm_tb_duv <= comm_write_c;
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tx_irq_tb_duv <= '1';
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dpram_addr_tb_duv <= 8;
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global_dpram_addr <= 8;
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test_case_ctrl_r <= monitor;
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-- Assert hibi full signal
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hibi_full_tb_duv <= '1';
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else
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assert false report "Cannot start test1, tx_status low" severity note;
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end if;
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when monitor =>
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tx_irq_tb_duv <= '0';
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counter_r <= counter_r+1;
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if counter_r < 10 then
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test_case_ctrl_r <= monitor;
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else
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hibi_full_tb_duv <= '0';
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test_case_ctrl_r <= finish;
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end if;
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-- if tx_status_duv_tb = '1' then
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-- -- values read.
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-- amount_tb_duv <= 0;
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-- dpram_addr_tb_duv <= 0;
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-- comm_tb_duv <= comm_idle_c;
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-- -- lets test the full signal
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-- end if;
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when finish =>
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if tx_status_duv_tb = '1' then
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assert false report "test1 finished." severity note;
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test_ctrl_r <= test2;
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test_case_ctrl_r <= assign;
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counter_r <= 0;
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else
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test_case_ctrl_r <= finish;
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end if;
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when others => null;
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end case;
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when test2 =>
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-- Tests how multiple packets are transferred and
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-- how max values are treated.
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case test_case_ctrl_r is
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when assign =>
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-- we always go to trigger next, unless otherwise noted.
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test_case_ctrl_r <= trigger;
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-- assign new values
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if counter_r = 0 then
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new_amount_r <= 6;
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new_hibi_addr_r <= 6302;
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new_dpram_addr_r <= 400;
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elsif counter_r = 1 then
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new_amount_r <= 172;
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new_hibi_addr_r <= 30;
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new_dpram_addr_r <= 300;
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elsif counter_r = 2 then
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new_amount_r <= 1;
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new_hibi_addr_r <= 21;
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new_dpram_addr_r <= 323;
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elsif counter_r = 3 then
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new_amount_r <= 14;
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new_hibi_addr_r <= 54;
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new_dpram_addr_r <= 12;
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elsif counter_r = 4 then
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new_amount_r <= 6;
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new_hibi_addr_r <= 602;
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new_dpram_addr_r <= 40;
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elsif counter_r = 5 then
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new_amount_r <= 9;
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new_hibi_addr_r <= 64510;
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new_dpram_addr_r <= 511;
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else
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--stop the tests
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|
|
test_ctrl_r <= stop_tests;
|
335 |
|
|
test_case_ctrl_r <= assign;
|
336 |
|
|
end if;
|
337 |
|
|
|
338 |
|
|
counter_r <= counter_r+1;
|
339 |
|
|
|
340 |
|
|
when trigger =>
|
341 |
|
|
-- assign and trigger irq.
|
342 |
|
|
|
343 |
|
|
if tx_status_duv_tb = '1' then
|
344 |
|
|
global_amount_r <= new_amount_r;
|
345 |
|
|
amount_tb_duv <= new_amount_r;
|
346 |
|
|
global_hibi_addr_r <= new_hibi_addr_r;
|
347 |
|
|
global_comm_r <= comm_write_c;
|
348 |
|
|
comm_tb_duv <= comm_write_c;
|
349 |
|
|
tx_irq_tb_duv <= '1';
|
350 |
|
|
dpram_addr_tb_duv <= new_dpram_addr_r;
|
351 |
|
|
global_dpram_addr <= new_dpram_addr_r;
|
352 |
|
|
test_case_ctrl_r <= monitor;
|
353 |
|
|
-- deassert hibi full signal, just in case
|
354 |
|
|
hibi_full_tb_duv <= '0';
|
355 |
|
|
|
356 |
|
|
else
|
357 |
|
|
assert false report "Cannot start test, tx_status low" severity note;
|
358 |
|
|
end if;
|
359 |
|
|
|
360 |
|
|
when monitor =>
|
361 |
|
|
tx_irq_tb_duv <= '0';
|
362 |
|
|
-- if tx_status_duv_tb = '1' then
|
363 |
|
|
-- -- values read.
|
364 |
|
|
-- amount_tb_duv <= 0;
|
365 |
|
|
-- dpram_addr_tb_duv <= 0;
|
366 |
|
|
-- comm_tb_duv <= comm_idle_c;
|
367 |
|
|
-- lets test the full signal
|
368 |
|
|
test_case_ctrl_r <= finish;
|
369 |
|
|
-- end if;
|
370 |
|
|
|
371 |
|
|
when finish =>
|
372 |
|
|
if tx_status_duv_tb = '1' then
|
373 |
|
|
assert false report "test2 finished." severity note;
|
374 |
|
|
test_case_ctrl_r <= assign;
|
375 |
|
|
else
|
376 |
|
|
test_case_ctrl_r <= finish;
|
377 |
|
|
end if;
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
when others => null;
|
381 |
|
|
end case;
|
382 |
|
|
when test3 =>
|
383 |
|
|
when stop_tests =>
|
384 |
|
|
assert false report "All tests finished." severity failure;
|
385 |
|
|
when others => null;
|
386 |
|
|
end case;
|
387 |
|
|
end if;
|
388 |
|
|
end process test;
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
--
|
393 |
|
|
-- Checks whether data going to hibi is right
|
394 |
|
|
--
|
395 |
|
|
check_hibi : process (clk) -- (clk)
|
396 |
|
|
begin -- process check_hibi
|
397 |
|
|
if rst_n = '0' then
|
398 |
|
|
hibi_addr_came <= '0';
|
399 |
|
|
|
400 |
|
|
elsif clk = '1' and clk'event then
|
401 |
|
|
|
402 |
|
|
assert hibi_amount >= 0 report "Hibi amount negative - too much data" severity warning;
|
403 |
|
|
|
404 |
|
|
|
405 |
|
|
-- Not expecting more data
|
406 |
|
|
if hibi_amount = 0 then
|
407 |
|
|
hibi_addr_came <= '0';
|
408 |
|
|
end if;
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
-- DMA writes. Check the addr and data
|
412 |
|
|
if hibi_we_duv_tb = '1' then
|
413 |
|
|
|
414 |
|
|
if hibi_comm_duv_tb /= global_comm_r then
|
415 |
|
|
assert false report "Hibi command failure - expected" & str(global_comm_r) severity warning;
|
416 |
|
|
end if;
|
417 |
|
|
|
418 |
|
|
|
419 |
|
|
if hibi_av_duv_tb = '1' then
|
420 |
|
|
-- DMA writes addr
|
421 |
|
|
|
422 |
|
|
-- Address valid should not come before we have received all the data
|
423 |
|
|
if hibi_amount = 0 then
|
424 |
|
|
if hibi_data_duv_tb = global_hibi_addr_r then
|
425 |
|
|
hibi_addr_came <= '1';
|
426 |
|
|
hibi_amount <= global_amount_r;
|
427 |
|
|
assert false report "Hibi addr OK " & str(hibi_data_duv_tb) severity note;
|
428 |
|
|
|
429 |
|
|
else
|
430 |
|
|
assert false report "Hibi address error, expected " & str(global_hibi_addr_r)
|
431 |
|
|
& ", but got " & str(hibi_data_duv_tb)
|
432 |
|
|
severity warning;
|
433 |
|
|
end if;
|
434 |
|
|
|
435 |
|
|
else
|
436 |
|
|
assert false report "Hibi data failure, address came before prev transfer is completed" severity warning;
|
437 |
|
|
end if;
|
438 |
|
|
|
439 |
|
|
else
|
440 |
|
|
-- DMA writes data
|
441 |
|
|
-- Data must be correct and come after addr
|
442 |
|
|
|
443 |
|
|
if hibi_addr_came = '1' then
|
444 |
|
|
if hibi_data_duv_tb = hibi_data_counter_r then
|
445 |
|
|
assert false report "Hibi data OK " & str(hibi_data_duv_tb) severity note;
|
446 |
|
|
|
447 |
|
|
hibi_data_counter_r <= hibi_data_counter_r+1;
|
448 |
|
|
hibi_amount <= hibi_amount-1;
|
449 |
|
|
if hibi_amount = 1 then
|
450 |
|
|
hibi_addr_came <= '0';
|
451 |
|
|
end if;
|
452 |
|
|
else
|
453 |
|
|
assert false report "Hibi data error, expexted " & str(hibi_data_counter_r)
|
454 |
|
|
& ", but got " & str(hibi_data_duv_tb)
|
455 |
|
|
severity warning;
|
456 |
|
|
end if;
|
457 |
|
|
|
458 |
|
|
else
|
459 |
|
|
assert false report "Data " & str(hibi_data_duv_tb) & " came before an address" severity warning;
|
460 |
|
|
end if;
|
461 |
|
|
end if;
|
462 |
|
|
|
463 |
|
|
end if;
|
464 |
|
|
end if;
|
465 |
|
|
|
466 |
|
|
end process check_hibi;
|
467 |
|
|
|
468 |
|
|
|
469 |
|
|
--
|
470 |
|
|
--
|
471 |
|
|
--
|
472 |
|
|
check_avalon : process (clk2, rst_n)
|
473 |
|
|
variable waitreq_cnt_r : integer := 0;
|
474 |
|
|
variable expected_ava_addr_v : integer := -1;
|
475 |
|
|
|
476 |
|
|
begin -- process check_avalon
|
477 |
|
|
if rst_n = '0' then
|
478 |
|
|
-- reset added 2011-11-11, ES
|
479 |
|
|
avalon_readdatavalid_tb_duv <= '0';
|
480 |
|
|
avalon_waitrequest_tb_duv <= '0';
|
481 |
|
|
|
482 |
|
|
--elsif clk2'event and clk2 = '1' then -- rising clock edge
|
483 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
484 |
|
|
|
485 |
|
|
--assert avalon_amount >= 0 report "avalon amount negative - tried to read too much data" severity warning;
|
486 |
|
|
|
487 |
|
|
avalon_last_addr <= to_integer(unsigned(avalon_addr_duv_tb));
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
-- DMA reads memory
|
491 |
|
|
if avalon_read_duv_tb = '1' then
|
492 |
|
|
if avalon_waitrequest_tb_duv = '0' then
|
493 |
|
|
|
494 |
|
|
avalon_readdatavalid_tb_duv <= '1';
|
495 |
|
|
|
496 |
|
|
|
497 |
|
|
-- Calculate the expected address
|
498 |
|
|
expected_ava_addr_v := global_dpram_addr + avalon_addr_counter_r; --es
|
499 |
|
|
|
500 |
|
|
if (expected_ava_addr_v) = (2**addr_width_c-2) then
|
501 |
|
|
avalon_addr_counter_r <= 0 - global_dpram_addr;
|
502 |
|
|
elsif (expected_ava_addr_v) = (2**addr_width_c-1) then
|
503 |
|
|
-- odd number (eg. 511) overflow, add one.
|
504 |
|
|
avalon_addr_counter_r <= 1 - global_dpram_addr;
|
505 |
|
|
else
|
506 |
|
|
avalon_addr_counter_r <= avalon_addr_counter_r + addr_offset_c;
|
507 |
|
|
end if;
|
508 |
|
|
|
509 |
|
|
-- Check addr
|
510 |
|
|
assert expected_ava_addr_v = avalon_addr_duv_tb report "Avalon address error, expected "
|
511 |
|
|
& str(expected_ava_addr_v)
|
512 |
|
|
& ", but got " & str(to_integer(unsigned(avalon_addr_duv_tb)))
|
513 |
|
|
severity warning;
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
|
517 |
|
|
-- Generate the data that comes from the "memory"
|
518 |
|
|
if avalon_addr_sent = '0' then
|
519 |
|
|
-- 2011-11-11 not sending addr anymore in the beginning
|
520 |
|
|
-- modifcation is prograa, not yet complete....
|
521 |
|
|
avalon_readdata_tb_duv <= avalon_data_counter_r;
|
522 |
|
|
avalon_data_counter_r <= avalon_data_counter_r+1;
|
523 |
|
|
avalon_addr_sent <= '1';
|
524 |
|
|
avalon_amount <= global_amount_r;
|
525 |
|
|
-- -- first slot contains address
|
526 |
|
|
-- avalon_readdata_tb_duv <= global_hibi_addr_r;
|
527 |
|
|
-- avalon_addr_sent <= '1';
|
528 |
|
|
-- avalon_amount <= global_amount_r;
|
529 |
|
|
|
530 |
|
|
else
|
531 |
|
|
-- now the data
|
532 |
|
|
if avalon_last_addr = avalon_addr_duv_tb then
|
533 |
|
|
avalon_readdata_tb_duv <= avalon_data_counter_r;
|
534 |
|
|
avalon_data_counter_r <= avalon_data_counter_r;
|
535 |
|
|
avalon_amount <= avalon_amount;
|
536 |
|
|
else
|
537 |
|
|
avalon_readdata_tb_duv <= avalon_data_counter_r;
|
538 |
|
|
avalon_data_counter_r <= avalon_data_counter_r+1;
|
539 |
|
|
avalon_amount <= avalon_amount-1;
|
540 |
|
|
|
541 |
|
|
end if;
|
542 |
|
|
|
543 |
|
|
if avalon_amount = 1 then
|
544 |
|
|
-- next we expect that a new packet should be sent.
|
545 |
|
|
avalon_addr_sent <= '0';
|
546 |
|
|
avalon_addr_counter_r <= 0;
|
547 |
|
|
end if;
|
548 |
|
|
|
549 |
|
|
end if;
|
550 |
|
|
|
551 |
|
|
end if;
|
552 |
|
|
else
|
553 |
|
|
-- Not reading
|
554 |
|
|
avalon_readdatavalid_tb_duv <= '0';
|
555 |
|
|
end if;
|
556 |
|
|
|
557 |
|
|
|
558 |
|
|
|
559 |
|
|
-- Generate occasional wait requests to DMA
|
560 |
|
|
avalon_waitrequest_tb_duv <= '0'; -- was always
|
561 |
|
|
waitreq_cnt_r := waitreq_cnt_r +1;
|
562 |
|
|
-- generate waitreq
|
563 |
|
|
if waitreq_cnt_r = wait_req_freq_c then
|
564 |
|
|
avalon_waitrequest_tb_duv <= '1' and avalon_read_duv_tb;
|
565 |
|
|
waitreq_cnt_r := 0;
|
566 |
|
|
end if;
|
567 |
|
|
|
568 |
|
|
|
569 |
|
|
end if; -- rst/clk
|
570 |
|
|
end process check_avalon;
|
571 |
|
|
|
572 |
|
|
|
573 |
|
|
--
|
574 |
|
|
-- Generate clocks and reset
|
575 |
|
|
--
|
576 |
|
|
CLOCK1 : process -- generate clock signal for design
|
577 |
|
|
variable clktmp : std_logic := '0';
|
578 |
|
|
begin
|
579 |
|
|
wait for PERIOD/2;
|
580 |
|
|
clktmp := not clktmp;
|
581 |
|
|
clk <= clktmp;
|
582 |
|
|
end process CLOCK1;
|
583 |
|
|
|
584 |
|
|
-- clk2 <= clk after PERIOD/4; -- 2011-11-15 ES
|
585 |
|
|
|
586 |
|
|
-- different phase for the avalon bus
|
587 |
|
|
CLOCK2 : process -- generate clock signal for design
|
588 |
|
|
variable clk2tmp : std_logic := '0';
|
589 |
|
|
begin
|
590 |
|
|
clk2tmp := not clk2tmp;
|
591 |
|
|
clk2 <= clk2tmp;
|
592 |
|
|
wait for PERIOD/2;
|
593 |
|
|
end process CLOCK2;
|
594 |
|
|
|
595 |
|
|
RESET : process
|
596 |
|
|
begin
|
597 |
|
|
rst_n <= '0'; -- Reset the testsystem
|
598 |
|
|
wait for 6*PERIOD; -- Wait
|
599 |
|
|
rst_n <= '1'; -- de-assert reset
|
600 |
|
|
wait;
|
601 |
|
|
end process RESET;
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
end rtl;
|