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lanttu |
-------------------------------------------------------------------------------
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-- Title : Testbench for design "n2h2_tx"
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-- Project :
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-------------------------------------------------------------------------------
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-- File : tb_n2h2_tx.vhd
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-- Author : kulmala3
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-- Created : 30.03.2005
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-- Last update: 2012-01-12
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-- Description: DMA reads data from memory and writes them to
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-- HIBI. Values are just running numbers and checked automatically.
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2005
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 30.03.2005 1.0 AK Created
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Funbase IP library Copyright (C) 2011 TUT Department of Computer Systems
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--
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-- This file is part of HIBI
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- either version 2.1 of the License, or (at your option) any
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-- later version.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.opencores.org/lgpl.shtml
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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entity tb_n2h2_tx is
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end tb_n2h2_tx;
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-------------------------------------------------------------------------------
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architecture rtl of tb_n2h2_tx is
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-- component generics
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constant data_width_g : integer := 32;
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constant amount_width_g : integer := 16;
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constant wait_between_sends_c : integer := 2; -- unit: cycles
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constant hibi_full_c : integer := 2;
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constant avalon_waitr_c : integer := 7;
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constant amount_max_c : integer := 63; -- longest transfer in words
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constant incr_hibi_full_after_c : time := 1000000 ns; -- how often HIBI
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-- goes full
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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-- clock and reset
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signal Clk : std_logic;
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signal Clk2 : std_logic; -- turha kello?
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signal Rst_n : std_logic;
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constant Period : time := 10 ns;
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type main_control_type is (idle, send, wait_one);
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signal main_ctrl_r : main_control_type;
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signal amount_r : std_logic_vector(amount_width_g-1 downto 0);
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signal mem_addr_r : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_addr_from_tx : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_re_from_tx : std_logic;
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signal avalon_readdata_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
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signal avalon_waitrequest_to_tx : std_logic;
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signal avalon_waitrequest_to_tx2 : std_logic;
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signal avalon_readdatavalid_to_tx : std_logic;
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signal hibi_data_from_tx : std_logic_vector(data_width_g-1 downto 0);
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signal hibi_av_from_tx : std_logic;
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signal hibi_full_to_tx : std_logic := '0';
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signal hibi_comm_from_tx : std_logic_vector(4 downto 0);
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signal hibi_we_from_tx : std_logic;
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-- Configuration signals
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signal tx_comm_to_tx : std_logic_vector(4 downto 0) := (others => '0');
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signal tx_hibi_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
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signal tx_ram_addr_to_tx : std_logic_vector(data_width_g-1 downto 0) := (others => '0');
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signal tx_amount_to_tx : std_logic_vector(amount_width_g-1 downto 0) := (others => '0');
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signal tx_start_to_tx : std_logic := '0';
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signal tx_status_done_from_tx : std_logic;
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-----------------------------------------------------------------------------
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-- Memory and Avalon
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-----------------------------------------------------------------------------
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constant rom_data_file_name_g : string := "ram_init.dat";
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constant output_file_name_g : string := "ram_contents.dat";
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constant write_trigger_g : natural := 16#6543#; -- RAM gets dumped to file
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constant ram_addr_width_g : integer := 16;
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signal cs1_n_to_ram : std_logic;
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signal cs2_to_ram : std_logic;
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signal addr_to_ram : std_logic_vector(ram_addr_width_g-1 downto 0);
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signal data_inout_ram : std_logic_vector(data_width_g-1 downto 0);
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signal we_n_to_ram : std_logic;
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signal oe_n_to_ram : std_logic;
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signal delayed_data_from_ram_r : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_ready_r : std_logic;
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-----------------------------------------------------------------------------
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-- Signal for modeling HIBI
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-----------------------------------------------------------------------------
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signal hibi_addr_r : std_logic_vector(data_width_g-1 downto 0);
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signal hibi_amount_r : std_logic_vector(amount_width_g-1 downto 0);
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signal hibi_data_r : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_addr_r : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_data_r : std_logic_vector(data_width_g-1 downto 0);
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signal avalon_amount_r : std_logic_vector(amount_width_g-1 downto 0);
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signal wait_cnt_r : integer range 0 to wait_between_sends_c;
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signal avalon_waitr_cnt_r : integer range 0 to avalon_waitr_c-1;
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signal hibi_we_was_up_r : std_logic;
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-- signal hibi_full_cnt_r : integer range 0 to hibi_full_c;
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signal hibi_full_cnt_r : integer;
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signal hibi_ready_r : std_logic;
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signal hibi_full_up_cc : integer := 0;
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begin -- rtl
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-----------------------------------------------------------------------------
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-- DUT component instantiation
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--
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-----------------------------------------------------------------------------
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DUT : entity work.hpd_tx_control
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generic map (
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data_width_g => data_width_g,
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amount_width_g => amount_width_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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avalon_addr_out => avalon_addr_from_tx,
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avalon_re_out => avalon_re_from_tx,
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avalon_readdata_in => avalon_readdata_to_tx,
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avalon_waitrequest_in => avalon_waitrequest_to_tx2,
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avalon_readdatavalid_in => avalon_readdatavalid_to_tx,
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hibi_data_out => hibi_data_from_tx,
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hibi_av_out => hibi_av_from_tx,
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hibi_full_in => hibi_full_to_tx,
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hibi_comm_out => hibi_comm_from_tx,
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hibi_we_out => hibi_we_from_tx,
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tx_start_in => tx_start_to_tx,
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tx_status_done_out => tx_status_done_from_tx,
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tx_comm_in => tx_comm_to_tx,
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tx_hibi_addr_in => tx_hibi_addr_to_tx,
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tx_ram_addr_in => tx_ram_addr_to_tx,
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tx_amount_in => tx_amount_to_tx);
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-----------------------------------------------------------------------------
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-- Give commands to the tested block n2h2_tx
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-- Asks to send longer and longer transfer
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------------------------------------------------------------------------------
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test : process (clk, rst_n)
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begin -- process test
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if rst_n = '0' then -- asynchronous reset (active low)
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tx_start_to_tx <= '0';
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tx_hibi_addr_to_tx <= X"0000ffff";
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tx_comm_to_tx <= (others => 'Z'); --'0');
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tx_ram_addr_to_tx <= (others => 'Z'); -- '0');
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tx_amount_to_tx <= (others => 'Z'); -- '0');
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wait_cnt_r <= 0;
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main_ctrl_r <= idle;
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amount_r <= conv_std_logic_vector(1, amount_width_g); --(others => '0');
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mem_addr_r <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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case main_ctrl_r is
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when idle =>
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-- Wait that previous tx is ready and then few cycles more.
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-- Increase the source memory address for every transfer
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tx_start_to_tx <= '0';
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if tx_status_done_from_tx = '1' then
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wait_cnt_r <= wait_cnt_r+1;
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if wait_cnt_r = wait_between_sends_c-1 then
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wait_cnt_r <= 0;
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main_ctrl_r <= send;
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if conv_integer(amount_r) > 1 then
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mem_addr_r <= mem_addr_r+conv_integer(tx_amount_to_tx)*4;
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else
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mem_addr_r <= mem_addr_r+conv_integer(tx_amount_to_tx)*4;
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end if;
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end if;
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end if;
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when send =>
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-- Ask to send a new transfer
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-- Increase the mem addr, hibi addr
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tx_start_to_tx <= '1';
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tx_ram_addr_to_tx <= mem_addr_r;
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tx_hibi_addr_to_tx <= tx_hibi_addr_to_tx+1;
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tx_amount_to_tx <= amount_r;
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tx_comm_to_tx <= "00010";
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-- Increase transfer length for the next time
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if conv_integer(amount_r) >= amount_max_c then
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amount_r <= conv_std_logic_vector(1, amount_width_g);
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else
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amount_r <= amount_r+1;
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end if;
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-- Loop back to idle state
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main_ctrl_r <= idle;
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when others =>
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end case;
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end if;
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end process test;
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-- avalon_readdata_to_tx <= avalon_data_r;
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-----------------------------------------------------------------------------
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-- Instantiate memory block
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------------------------------------------------------------------------------
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sram_scalable_1 : entity work.sram_scalable
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generic map (
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rom_data_file_name_g => rom_data_file_name_g,
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output_file_name_g => output_file_name_g,
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write_trigger_g => write_trigger_g,
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addr_width_g => ram_addr_width_g,
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data_width_g => data_width_g)
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port map (
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cs1_n_in => cs1_n_to_ram,
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cs2_in => cs2_to_ram,
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addr_in => addr_to_ram,
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data_inout => data_inout_ram,
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we_n_in => we_n_to_ram,
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oe_n_in => oe_n_to_ram
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);
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-----------------------------------------------------------------------------
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-- Imitate Avalon switch fabric between mem and n2h2_tx:
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-- - delay the addr going to memory by one cycle
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-- - delay the data coming from memory by one cycle
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------------------------------------------------------------------------------
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cs1_n_to_ram <= '0'; -- avalon_waitrequest_to_tx;
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cs2_to_ram <= avalon_re_from_tx;
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addr_to_ram <= conv_std_logic_vector(conv_integer(avalon_addr_from_tx)/4, ram_addr_width_g);
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avalon_waitrequest_to_tx2 <= avalon_waitrequest_to_tx or (not avalon_re_from_tx);
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avalon_readdata_to_tx <= delayed_data_from_ram_r;
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delay_valid : process (clk, rst_n)
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begin -- process delay_valid
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if rst_n = '0' then -- asynchronous reset (active low)
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elsif clk'event and clk = '1' then -- rising clock edge
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-- memory latency 2 (note below the same signal assignment)
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avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
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end if;
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end process delay_valid;
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-- memory latency 1
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-- avalon_readdatavalid_to_tx <= not avalon_waitrequest_to_tx2;
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we_n_to_ram <= '1';
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oe_n_to_ram <= '0';
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avalon : process (clk2, rst_n)
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begin -- process avalon
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if rst_n = '0' then -- asynchronous reset (active low)
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avalon_waitrequest_to_tx <= '1';
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delayed_data_from_ram_r <= (others => 'Z'); --data_inout_ram;
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avalon_waitr_cnt_r <= 0;
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elsif clk'event and clk = '1' then -- rising clock edge
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if tx_start_to_tx = '1' then
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avalon_addr_r <= mem_addr_r;
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end if;
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delayed_data_from_ram_r <= data_inout_ram;
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if avalon_re_from_tx = '1' then
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if avalon_waitr_cnt_r = avalon_waitr_c-1 then
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avalon_waitr_cnt_r <= 0;
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avalon_waitrequest_to_tx <= '1';
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else
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avalon_waitr_cnt_r <= avalon_waitr_cnt_r+1;
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avalon_waitrequest_to_tx <= '0';
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end if;
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else
|
341 |
|
|
avalon_waitrequest_to_tx <= '1';
|
342 |
|
|
end if;
|
343 |
|
|
end if;
|
344 |
|
|
--avalon_waitrequest_to_tx <= '0';
|
345 |
|
|
end process avalon;
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
-----------------------------------------------------------------------------
|
349 |
|
|
-- Imitate the HIBI wrapper that gets the data from n2h2_tx
|
350 |
|
|
------------------------------------------------------------------------------
|
351 |
|
|
hibi : process (clk, rst_n)
|
352 |
|
|
begin -- process hibi
|
353 |
|
|
if rst_n = '0' then -- asynchronous reset (active low)
|
354 |
|
|
hibi_addr_r <= X"0000ffff";
|
355 |
|
|
hibi_full_to_tx <= '1';
|
356 |
|
|
hibi_data_r <= (others => '0');
|
357 |
|
|
hibi_amount_r <= (others => '0');
|
358 |
|
|
hibi_full_cnt_r <= 0;
|
359 |
|
|
hibi_we_was_up_r <= '1';
|
360 |
|
|
|
361 |
|
|
elsif clk'event and clk = '1' then -- rising clock edge
|
362 |
|
|
|
363 |
|
|
-- Generate full signal
|
364 |
|
|
if hibi_we_was_up_r = '1' then
|
365 |
|
|
hibi_full_cnt_r <= hibi_full_cnt_r+1;
|
366 |
|
|
hibi_full_to_tx <= '1';
|
367 |
|
|
if hibi_full_cnt_r = hibi_full_up_cc then
|
368 |
|
|
hibi_full_to_tx <= '0';
|
369 |
|
|
hibi_full_cnt_r <= 0;
|
370 |
|
|
hibi_we_was_up_r <= '0';
|
371 |
|
|
end if;
|
372 |
|
|
end if;
|
373 |
|
|
|
374 |
|
|
-- Take and check the incoming data
|
375 |
|
|
if hibi_we_from_tx = '1' then
|
376 |
|
|
if hibi_full_up_cc > 0 then
|
377 |
|
|
hibi_full_to_tx <= '1';
|
378 |
|
|
end if;
|
379 |
|
|
hibi_we_was_up_r <= '1';
|
380 |
|
|
|
381 |
|
|
assert hibi_comm_from_tx /= "00000" report "Error. DMA sets comm=idle" severity error;
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
if hibi_av_from_tx = '1' then
|
386 |
|
|
-- Check incoming address
|
387 |
|
|
-- +1 because of the main test program value
|
388 |
|
|
assert hibi_addr_r+1 = hibi_data_from_tx report "hibi addr error" severity error;
|
389 |
|
|
hibi_addr_r <= hibi_addr_r+1;
|
390 |
|
|
|
391 |
|
|
else
|
392 |
|
|
-- Check incoming data
|
393 |
|
|
assert avalon_readdata_to_tx = hibi_data_from_tx report "hibi data error" severity error;
|
394 |
|
|
|
395 |
|
|
if hibi_data_r = 2**ram_addr_width_g-1 then
|
396 |
|
|
hibi_data_r <= (others => '0');
|
397 |
|
|
else
|
398 |
|
|
hibi_data_r <= hibi_data_r+1;
|
399 |
|
|
end if;
|
400 |
|
|
|
401 |
|
|
hibi_amount_r <= hibi_amount_r+1;
|
402 |
|
|
assert hibi_amount_r <= tx_amount_to_tx report "too many data" severity error;
|
403 |
|
|
end if;
|
404 |
|
|
|
405 |
|
|
else
|
406 |
|
|
-- DMA does not write to HIBI
|
407 |
|
|
if main_ctrl_r = send then
|
408 |
|
|
hibi_amount_r <= (others => '0');
|
409 |
|
|
end if;
|
410 |
|
|
end if;
|
411 |
|
|
|
412 |
|
|
end if;
|
413 |
|
|
end process hibi;
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
-----------------------------------------------------------------------------
|
417 |
|
|
--
|
418 |
|
|
------------------------------------------------------------------------------
|
419 |
|
|
full_control : process
|
420 |
|
|
begin -- process full_control
|
421 |
|
|
wait for incr_hibi_full_after_c;
|
422 |
|
|
hibi_full_up_cc <= hibi_full_up_cc+1;
|
423 |
|
|
end process full_control;
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
|
427 |
|
|
-----------------------------------------------------------------------------
|
428 |
|
|
-- Generate clokcs and reset
|
429 |
|
|
------------------------------------------------------------------------------
|
430 |
|
|
CLOCK1 : process -- generate clock signal for design
|
431 |
|
|
variable clktmp : std_logic := '0';
|
432 |
|
|
begin
|
433 |
|
|
wait for PERIOD/2;
|
434 |
|
|
clktmp := not clktmp;
|
435 |
|
|
Clk <= clktmp;
|
436 |
|
|
end process CLOCK1;
|
437 |
|
|
|
438 |
|
|
CLOCK2 : process -- generate clock signal for design
|
439 |
|
|
variable clktmp : std_logic := '0';
|
440 |
|
|
begin
|
441 |
|
|
clktmp := not clktmp;
|
442 |
|
|
Clk2 <= clktmp;
|
443 |
|
|
wait for PERIOD/2;
|
444 |
|
|
end process CLOCK2;
|
445 |
|
|
|
446 |
|
|
RESET : process
|
447 |
|
|
begin
|
448 |
|
|
Rst_n <= '0'; -- Reset the testsystem
|
449 |
|
|
wait for 6*PERIOD; -- Wait
|
450 |
|
|
Rst_n <= '1'; -- de-assert reset
|
451 |
|
|
wait;
|
452 |
|
|
end process RESET;
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
|
456 |
|
|
|
457 |
|
|
end rtl;
|