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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi_pe_dma/] [1.0/] [tb/] [blocks/] [wave_tb_n2h2_rx.do] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu 
onerror {resume}
2 
quietly WaveActivateNextPane {} 0
3 
add wave -noupdate /tb_n2h2_rx/system_control_r
4 
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0) -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(0)(63) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(62) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(61) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(60) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(59) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(58) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(57) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(56) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(55) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(54) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(53) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(52) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(51) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(50) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(49) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(48) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(47) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(46) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(45) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(44) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(43) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(42) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(41) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(40) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(39) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(38) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(37) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(36) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(35) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(34) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(33) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(32) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(31) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(30) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(29) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(28) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(27) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(26) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(25) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(24) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(23) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(22) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(21) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(20) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(19) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(18) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(17) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(16) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(15) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(14) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(13) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(12) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(11) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(10) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(9) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(8) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(7) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(6) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(5) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(4) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(3) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(0) -radix hexadecimal}}}} -subitemconfig {/tb_n2h2_rx/my_own_addr(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0) {-height 15 -radix hexadecimal -childformat {{/tb_n2h2_rx/my_own_addr(0)(63) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(62) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(61) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(60) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(59) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(58) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(57) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(56) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(55) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(54) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(53) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(52) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(51) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(50) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(49) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(48) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(47) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(46) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(45) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(44) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(43) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(42) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(41) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(40) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(39) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(38) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(37) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(36) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(35) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(34) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(33) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(32) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(31) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(30) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(29) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(28) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(27) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(26) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(25) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(24) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(23) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(22) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(21) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(20) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(19) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(18) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(17) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(16) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(15) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(14) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(13) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(12) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(11) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(10) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(9) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(8) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(7) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(6) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(5) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(4) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(3) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(2) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(1) -radix hexadecimal} {/tb_n2h2_rx/my_own_addr(0)(0) -radix hexadecimal}}} /tb_n2h2_rx/my_own_addr(0)(63) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(62) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(61) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(60) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(59) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(58) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(57) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(56) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(55) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(54) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(53) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(52) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(51) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(50) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(49) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(48) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(47) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(46) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(45) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(44) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(43) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(42) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(41) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(40) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(39) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(38) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(37) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(36) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(35) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(34) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(33) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(32) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/my_own_addr(0)(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/my_own_addr
5 
add wave -noupdate /tb_n2h2_rx/rx_irq_from_dma
6 
add wave -noupdate /tb_n2h2_rx/irq_was_up
7 
add wave -noupdate /tb_n2h2_rx/irq_counter
8 
add wave -noupdate -divider {Configuring the DMA}
9 
add wave -noupdate /tb_n2h2_rx/clk
10 
add wave -noupdate /tb_n2h2_rx/clk2
11 
add wave -noupdate /tb_n2h2_rx/rst_n
12 
add wave -noupdate /tb_n2h2_rx/init_to_cfgw
13 
add wave -noupdate /tb_n2h2_rx/start_to_cfgw
14 
add wave -noupdate /tb_n2h2_rx/avalon_cfg_cs_to_dma
15 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_addr_to_dma
16 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_writedata_to_dma
17 
add wave -noupdate /tb_n2h2_rx/avalon_cfg_we_to_dma
18 
add wave -noupdate /tb_n2h2_rx/done_from_cfgw
19 
add wave -noupdate /tb_n2h2_rx/avalon_reader_rst_n
20 
add wave -noupdate /tb_n2h2_rx/start_to_cfgr
21 
add wave -noupdate /tb_n2h2_rx/avalon_cfg_cs_to_dma
22 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_addr_to_dma
23 
add wave -noupdate /tb_n2h2_rx/avalon_cfg_re_to_dma
24 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_cfg_readdata_from_dma
25 
add wave -noupdate /tb_n2h2_rx/done_from_cfgr
26 
add wave -noupdate /tb_n2h2_rx/tx_start_from_dma
27 
add wave -noupdate /tb_n2h2_rx/tx_status_done_to_dma
28 
add wave -noupdate /tb_n2h2_rx/not_my_addr_from_readers
29 
add wave -noupdate -divider {HIBI -> DMA}
30 
add wave -noupdate /tb_n2h2_rx/clk
31 
add wave -noupdate /tb_n2h2_rx/rst_n
32 
add wave -noupdate /tb_n2h2_rx/hibi_sender_rst_n
33 
add wave -noupdate /tb_n2h2_rx/hibi_sender_start
34 
add wave -noupdate /tb_n2h2_rx/hibi_av_to_dma
35 
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/hibi_data_to_dma(63) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(62) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(61) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(60) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(59) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(58) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(57) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(56) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(55) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(54) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(53) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(52) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(51) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(50) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(49) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(48) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(47) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(46) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(45) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(44) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(43) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(42) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(41) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(40) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(39) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(38) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(37) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(36) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(35) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(34) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(33) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(32) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(31) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(30) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(29) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(28) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(27) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(26) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(25) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(24) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(23) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(22) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(21) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(20) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(19) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(18) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(17) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(16) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(15) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(14) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(13) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(12) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(11) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(10) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(9) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(8) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(7) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(6) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(5) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(4) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(3) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(2) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(1) -radix hexadecimal} {/tb_n2h2_rx/hibi_data_to_dma(0) -radix hexadecimal}} -subitemconfig {/tb_n2h2_rx/hibi_data_to_dma(63) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(62) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(61) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(60) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(59) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(58) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(57) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(56) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(55) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(54) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(53) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(52) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(51) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(50) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(49) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(48) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(47) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(46) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(45) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(44) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(43) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(42) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(41) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(40) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(39) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(38) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(37) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(36) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(35) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(34) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(33) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(32) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/hibi_data_to_dma(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/hibi_data_to_dma
36 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/hibi_comm_to_dma
37 
add wave -noupdate /tb_n2h2_rx/hibi_re_from_dma
38 
add wave -noupdate /tb_n2h2_rx/hibi_empty_to_dma
39 
add wave -noupdate /tb_n2h2_rx/pause_hibi_send
40 
add wave -noupdate /tb_n2h2_rx/pause_ack_hibi_send
41 
add wave -noupdate -divider {DMA -> mem}
42 
add wave -noupdate /tb_n2h2_rx/clk
43 
add wave -noupdate /tb_n2h2_rx/rst_n
44 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_addr_from_dma
45 
add wave -noupdate /tb_n2h2_rx/avalon_we_from_dma
46 
add wave -noupdate /tb_n2h2_rx/avalon_be_from_dma
47 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/avalon_writedata_from_dma
48 
add wave -noupdate /tb_n2h2_rx/avalon_waitrequest_to_dma
49 
add wave -noupdate /tb_n2h2_rx/avalon_waitreqvec_to_dma
50 
add wave -noupdate -divider {DUT rx}
51 
add wave -noupdate /tb_n2h2_rx/DUT/clk
52 
add wave -noupdate /tb_n2h2_rx/DUT/rst_n
53 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_addr_in
54 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_writedata_in
55 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_we_in
56 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_cfg_readdata_out
57 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_re_in
58 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_cfg_cs_in
59 
add wave -noupdate /tb_n2h2_rx/DUT/rx_irq_out
60 
add wave -noupdate /tb_n2h2_rx/DUT/tx_start_out
61 
add wave -noupdate /tb_n2h2_rx/DUT/tx_comm_out
62 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_mem_addr_out
63 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_hibi_addr_out
64 
add wave -noupdate /tb_n2h2_rx/DUT/tx_amount_out
65 
add wave -noupdate /tb_n2h2_rx/DUT/tx_status_done_in
66 
add wave -noupdate /tb_n2h2_rx/DUT/clk
67 
add wave -noupdate /tb_n2h2_rx/DUT/rst_n
68 
add wave -noupdate -radix unsigned /tb_n2h2_rx/DUT/avalon_addr_out
69 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_we_out
70 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_out
71 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_writedata_out
72 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_waitrequest_in
73 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/hibi_data_in
74 
add wave -noupdate /tb_n2h2_rx/DUT/hibi_av_in
75 
add wave -noupdate /tb_n2h2_rx/DUT/hibi_empty_in
76 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/hibi_comm_in
77 
add wave -noupdate /tb_n2h2_rx/DUT/hibi_re_out
78 
add wave -noupdate /tb_n2h2_rx/DUT/clk
79 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/mem_addr_r
80 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/sender_addr_r
81 
add wave -noupdate -radix unsigned /tb_n2h2_rx/DUT/irq_amount_r
82 
add wave -noupdate /tb_n2h2_rx/DUT/control_r
83 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_mem_addr_r
84 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/tx_hibi_addr_r
85 
add wave -noupdate /tb_n2h2_rx/DUT/tx_amount_r
86 
add wave -noupdate /tb_n2h2_rx/DUT/tx_comm_r
87 
add wave -noupdate /tb_n2h2_rx/DUT/init_chan_r
88 
add wave -noupdate /tb_n2h2_rx/DUT/irq_chan_r
89 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/current_mem_addr_r
90 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/current_be_r
91 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_r
92 
add wave -noupdate /tb_n2h2_rx/DUT/status_r
93 
add wave -noupdate /tb_n2h2_rx/DUT/irq_reset_r
94 
add wave -noupdate /tb_n2h2_rx/DUT/hibi_re_r
95 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_we_r
96 
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx
97 
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx_irq_r
98 
add wave -noupdate /tb_n2h2_rx/DUT/unknown_rx_r
99 
add wave -noupdate -radix hexadecimal /tb_n2h2_rx/DUT/avalon_addr_r
100 
add wave -noupdate /tb_n2h2_rx/DUT/curr_chan_avalon_we_r
101 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_wes
102 
add wave -noupdate /tb_n2h2_rx/DUT/matches
103 
add wave -noupdate /tb_n2h2_rx/DUT/matches_cmb
104 
add wave -noupdate /tb_n2h2_rx/DUT/irq_ack_r
105 
add wave -noupdate -radix hexadecimal -childformat {{/tb_n2h2_rx/DUT/avalon_addr_temp(31) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(30) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(29) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(28) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(27) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(26) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(25) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(24) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(23) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(22) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(21) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(20) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(19) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(18) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(17) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(16) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(15) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(14) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(13) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(12) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(11) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(10) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(9) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(8) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(7) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(6) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(5) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(4) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(3) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(2) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(1) -radix hexadecimal} {/tb_n2h2_rx/DUT/avalon_addr_temp(0) -radix hexadecimal}} -subitemconfig {/tb_n2h2_rx/DUT/avalon_addr_temp(31) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(30) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(29) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(28) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(27) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(26) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(25) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(24) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(23) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(22) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(21) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(20) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(19) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(18) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(17) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(16) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(15) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(14) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(13) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(12) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(11) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(10) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(9) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(8) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(7) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(6) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(5) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(4) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(3) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(2) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(1) {-height 15 -radix hexadecimal} /tb_n2h2_rx/DUT/avalon_addr_temp(0) {-height 15 -radix hexadecimal}} /tb_n2h2_rx/DUT/avalon_addr_temp
106 
add wave -noupdate /tb_n2h2_rx/DUT/avalon_be_temp
107 
add wave -noupdate -divider {Dut ends}
108 
TreeUpdate [SetDefaultTree]
109 
WaveRestoreCursors {{Cursor 1} {759 ns} 0}
110 
configure wave -namecolwidth 274
111 
configure wave -valuecolwidth 100
112 
configure wave -justifyvalue left
113 
configure wave -signalnamewidth 1
114 
configure wave -snapdistance 10
115 
configure wave -datasetprefix 0
116 
configure wave -rowmargin 4
117 
configure wave -childrowmargin 2
118 
configure wave -gridoffset 0
119 
configure wave -gridperiod 1
120 
configure wave -griddelta 40
121 
configure wave -timeline 0
122 
configure wave -timelineunits ms
123 
update
124 
WaveRestoreZoom {506 ns} {1506 ns}

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