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-------------------------------------------------------------------------------
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-- Title : HIBI PE DMA - tx controller
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-- Project :
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-------------------------------------------------------------------------------
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-- File : hpd_tx_control.vhd
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-- Author : kulmala3
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-- Created : 2012-01-10
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-- Last update: 2012-02-08
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-- Description:
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--
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-------------------------------------------------------------------------------
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-- Copyright (c) 2005
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--
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 30.03.2005 1.0 AK Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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entity hpd_tx_control is
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generic (
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data_width_g : integer := 32;
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addr_width_g : integer := 32;
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words_width_g : integer := 16);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- Avalon master read interface
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avalon_addr_out : out std_logic_vector(addr_width_g-1 downto 0);
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avalon_re_out : out std_logic;
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avalon_readdata_in : in std_logic_vector(data_width_g-1 downto 0);
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avalon_waitrequest_in : in std_logic;
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avalon_readdatavalid_in : in std_logic;
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-- hibi write interface
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hibi_data_out : out std_logic_vector(data_width_g-1 downto 0);
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hibi_av_out : out std_logic;
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hibi_full_in : in std_logic;
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hibi_comm_out : out std_logic_vector(4 downto 0);
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hibi_we_out : out std_logic;
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-- DMA conf interface
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tx_start_in : in std_logic;
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tx_status_done_out : out std_logic;
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tx_comm_in : in std_logic_vector(4 downto 0);
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tx_hibi_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
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tx_ram_addr_in : in std_logic_vector(addr_width_g-1 downto 0);
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tx_words_in : in std_logic_vector(words_width_g-1 downto 0)
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);
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end hpd_tx_control;
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architecture rtl of hpd_tx_control is
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type control_states is (idle, transmit_addr, transmit, hfull);
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signal control_r : control_states;
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constant addr_offset_c : integer := data_width_g/8;
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signal addr_cnt_en : std_logic;
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signal addr_cnt_value : std_logic_vector(addr_width_g-1 downto 0);
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signal addr_cnt_load : std_logic;
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signal addr_r : std_logic_vector(addr_width_g-1 downto 0);
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signal words_cnt_en : std_logic;
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signal words_cnt_value : std_logic_vector(addr_width_g-1 downto 0);
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signal words_cnt_load : std_logic;
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signal words_r : std_logic_vector(addr_width_g-1 downto 0);
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signal addr_words_eq : std_logic;
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signal addr_to_stop : std_logic_vector(addr_width_g-1 downto 0);
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signal avalon_re : std_logic;
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signal start_re_r : std_logic;
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signal hibi_write_addr_r : std_logic;
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signal data_src_sel : std_logic;
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signal hibi_we : std_logic;
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signal hibi_stop_we_r : std_logic;
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begin -- rtl
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-----------------------------------------------------------------------------
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-- 1) waitrequest affects the data reading
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-- 2) readdatavalid data write to hibi
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-- 3) avalon side read must control the amount of data
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-- 4) whenever readdatavalid is asserted, data is written to HIBI
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-- 5) HIBI full is problematic. A counter must be added to see from which
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-- address we have succesfully read the data so far. We cannot
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-- save the data to register, because we are unaware of the latency.
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-- So when full comes, the read process from avalon must be started
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-- again.
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-- 6) write and read signals should be asynchronously controlled by
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-- signals from hibi and avalon in order to react as fast as possible.
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-- 7) after full the write should be ceased. readdatavalid from older data
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-- should be taken care of. Write continues only after read enable has
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-- been asserted again?
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-- 8) read from avalon must proceed as fast as possible. for example,
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-- start already when writing address to hibi. (at least one clock
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-- cycle latency expected, should be safe). Or after full.
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-- 9) data to hibi comes from either register input (address) or
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-- straight from the memory. mux is needed.
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-----------------------------------------------------------------------------
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hibi_comm_out <= tx_comm_in;
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avalon_addr_out <= addr_r;
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addr_cnt_s : process (clk, rst_n)
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begin -- process addr_cnt
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if rst_n = '0' then -- asynchronous reset (active low)
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addr_r <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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if addr_cnt_en = '1' then
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addr_r <= addr_r +
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std_logic_vector(to_unsigned(addr_offset_c, addr_width_g));
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elsif addr_cnt_load = '1' then
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addr_r <= addr_cnt_value;
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end if;
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end if;
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end process addr_cnt_s;
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addr_cnt_load <= (tx_start_in or hibi_full_in);
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addr_cnt : process (tx_ram_addr_in, words_r, tx_start_in)
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begin -- process addr_cnt
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if tx_start_in = '1' then
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-- addr from input
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addr_cnt_value <= tx_ram_addr_in;
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else
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-- addr from counter
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addr_cnt_value <= words_r;
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end if;
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end process addr_cnt;
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words_cnt : process (clk, rst_n)
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begin
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if rst_n = '0' then -- asynchronous reset (active low)
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words_r <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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if words_cnt_en = '1' then
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words_r <= words_r +
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std_logic_vector(to_unsigned(addr_offset_c, addr_width_g));
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elsif words_cnt_load = '1' then
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words_r <= words_cnt_value;
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end if;
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end if;
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end process words_cnt;
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-- words counted only when data is written
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words_cnt_en <= hibi_we and (not data_src_sel);
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-- hibi_we depends on readdatavalid and full + control signal for
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-- address writing
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-- start address writing right when the signal comes in.
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-- no old readdatavalids should be written if full is short.
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hibi_we_out <= hibi_we;
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hibi_we <= ((data_src_sel) or
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(avalon_readdatavalid_in and (not hibi_stop_we_r)))
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and (not hibi_full_in);
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data_src_sel <= tx_start_in or hibi_write_addr_r;
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hibi_av_out <= data_src_sel;
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addr_data : process (tx_hibi_addr_in, avalon_readdata_in, data_src_sel)
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begin -- process addr_data
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if data_src_sel = '1' then
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hibi_data_out <= (others => '0');
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hibi_data_out(addr_width_g-1 downto 0) <= tx_hibi_addr_in;
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else
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hibi_data_out <= avalon_readdata_in;
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end if;
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end process addr_data;
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-- if we're reading and not forced to wait,
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-- increase the address. we want to cease reading if hibi goes full
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-- (reload address)
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addr_cnt_en <= (avalon_re and (not avalon_waitrequest_in)) and
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(not hibi_full_in);
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avalon_re_out <= avalon_re;
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-- read enable depends on the words transferred, if a
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-- transmission is ongoing. shoot as soon as possible,
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-- whenever new transmission is assigned.
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avalon_re <= start_re_r;
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comparison : process (addr_r, addr_to_stop)
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begin -- process comparison
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if addr_r = addr_to_stop then
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addr_words_eq <= '1';
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else
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addr_words_eq <= '0';
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end if;
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end process comparison;
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addr_to_stop_p : process (tx_words_in, tx_ram_addr_in)
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begin -- process addr_to_stop
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addr_to_stop <= tx_ram_addr_in + std_logic_vector(
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resize(unsigned(tx_words_in)*addr_offset_c, addr_width_g));
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end process addr_to_stop_p;
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words_cnt_value <= tx_ram_addr_in;
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words_cnt_load <= tx_start_in;
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main : process (clk, rst_n)
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begin -- process main
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if rst_n = '0' then -- asynchronous reset (active low)
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control_r <= idle;
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start_re_r <= '0';
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hibi_write_addr_r <= '0';
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tx_status_done_out <= '1';
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hibi_stop_we_r <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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case control_r is
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when idle =>
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hibi_write_addr_r <= '0';
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start_re_r <= '0';
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tx_status_done_out <= '1';
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hibi_stop_we_r <= '1';
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if tx_start_in = '1' then
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-- avalon read address
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-- address which contents written to hibi
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tx_status_done_out <= '0';
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hibi_stop_we_r <= '0';
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if hibi_full_in = '0' then
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-- address will be transferred in this clock cycle
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control_r <= transmit;
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start_re_r <= '1';
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else
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hibi_write_addr_r <= '1';
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control_r <= transmit_addr;
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end if;
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end if;
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when transmit_addr =>
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-- if we're here, hibi was full
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if hibi_full_in = '0' then
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-- we wrote the addr
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start_re_r <= '1';
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control_r <= transmit;
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hibi_write_addr_r <= '0';
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else
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start_re_r <= '0';
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control_r <= transmit_addr;
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hibi_write_addr_r <= '1';
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end if;
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when transmit =>
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if hibi_full_in = '1' then
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start_re_r <= '0';
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control_r <= hfull;
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hibi_stop_we_r <= '1';
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else
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start_re_r <= '1';
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hibi_stop_we_r <= '0';
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control_r <= transmit;
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end if;
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-- if addr_words_eq = '1' and hibi_full_in = '0' then
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if addr_words_eq = '1' and hibi_we = '1' then
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control_r <= idle;
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-- stopped transferring
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tx_status_done_out <= '1';
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hibi_stop_we_r <= '1';
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end if;
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when hfull =>
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if hibi_full_in = '0' and avalon_readdatavalid_in = '0' then
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-- datavalid has to go down before proceed.
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-- so we make sure that no invalid data is written
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-- when there's a short full.
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start_re_r <= '1';
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hibi_stop_we_r <= '0';
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control_r <= transmit;
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else
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start_re_r <= '0';
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hibi_stop_we_r <= '1';
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control_r <= hfull;
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end if;
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when others => null;
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end case;
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end if;
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end process main;
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end rtl;
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