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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [drv/] [tut_n2h_regs.h] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu
/*
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* History:
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*    10/08/2005 by ollil
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*        + Copied minor modifications implemented by Ari.
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*          This fixed a crash bug in DCT HW based system
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*    03/10/2008 by tapiok
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*       fixed N2H_RX_IRQ_DIS
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*    08/2009 kojo2
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*       Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
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*                                  N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
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*/
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#ifndef __tut_n2h_regs_h_
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#define __tut_n2h_regs_h_
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#ifdef NIOS_II
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#include "io.h"
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#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
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#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
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#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
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#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
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#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
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#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
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#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
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#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
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#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
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#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
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#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
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#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
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#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
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#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
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#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
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#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
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#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
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#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
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#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
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#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
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#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
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#else 
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#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base)       \
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  {                                             \
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    volatile int * apu = (int*)base;            \
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    apu = apu + ((chan) << 4) + 1;              \
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    *apu=hibi_addr;                             \
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  }
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#define N2H_CHAN_MEM_ADDR(chan, addr, base)     \
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  {                                             \
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    volatile int * apu = (int*)base;            \
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    apu = apu + ((chan) << 4);                  \
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    *apu=addr;                                  \
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  }
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#define N2H_CHAN_AMOUNT(chan, amount, base)     \
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  {                                             \
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    volatile int * apu = (int*)base;            \
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    apu = apu + ((chan) << 4) + 2;              \
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    *apu=amount;                                \
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  }
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#define N2H_CHAN_INIT(chan, base)               \
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  {                                             \
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    volatile int * apu = (int*)base + 5;        \
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    *apu=1 << (chan);                           \
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  }
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#define N2H_RX_IRQ_ENA(base)                    \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    *apu= *apu | 0x2;                           \
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  }
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#define N2H_RX_IRQ_DIS(base)                    \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    *apu= *apu & 0xfffffffd;                    \
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  }
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#define N2H_GET_STAT_REG(var, base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    var = *apu >> 16;                           \
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  }
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#define N2H_GET_CONF_REG(var, base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    var = *apu & 0x0000ffff;                    \
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  }
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#define N2H_GET_INIT_REG(var, base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 5;        \
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    var = *apu;                                 \
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  }
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#define N2H_GET_IRQ_REG(var, base)              \
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  {                                             \
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    volatile int * apu = (int*)base + 7;        \
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    var = *apu;                                 \
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  }
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#define N2H_GET_CURR_PTR(var, chan, base)       \
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  {                                             \
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    volatile int * apu = (int*)base + 3;        \
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    apu = apu + ((chan) << 4);                  \
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    var = *apu;                                 \
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  }
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#define N2H_TX_MEM_ADDR(addr, base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 8;        \
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    *apu = addr;                                \
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  }
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#define N2H_TX_AMOUNT(amount, base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 9;        \
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    *apu = amount;                              \
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  }
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#define N2H_TX_HIBI_ADDR(haddr, base)           \
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  {                                             \
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    volatile int * apu = (int*)base + 11;       \
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    *apu = haddr;                               \
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  }
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#define N2H_TX_COMM(comm, base)                 \
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  {                                             \
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    volatile int * apu = (int*)base +10;        \
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    *apu = comm;                                \
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  }
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#define N2H_TX_COMM_WRITE(base)                 \
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  {                                             \
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    volatile int * apu = (int*)base + 10;       \
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    *apu = 2;                                   \
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  }
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#define N2H_TX_COMM_READ(base)                  \
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  {                                             \
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    volatile int * apu = (int*)base + 10;       \
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    *apu = 4;                                   \
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  }
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#define N2H_TX_COMM_WRITE_MSG(base)             \
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  {                                             \
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    volatile int * apu = (int*)base + 10;       \
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    *apu = 3;                                   \
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  }
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#define N2H_TX_START(base)                      \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    *apu = *apu | 0x1;                          \
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    *apu = *apu & 0xfffffffe;                   \
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  }
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#define N2H_GET_TX_DONE(y, base)                \
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  {                                             \
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    volatile int * apu = (int*)base + 4;        \
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    y = *apu >> 16;                             \
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    y = y & 0x1;                                \
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  }
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#define N2H_RX_CLEAR_IRQ(chan, base)            \
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  {                                             \
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    volatile int * apu = (int*)base + 7;        \
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    *apu = 1 << (chan);                         \
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  }
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#endif
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#ifdef API
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extern void N2H_INIT_ISR();
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extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
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extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
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extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
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#endif
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/*
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* DMA engine configuration
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*/
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extern void N2H_CHAN_CONF( int channel,
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                           int mem_addr,
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                           int rx_addr,
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                           int amount,
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                           int* base );
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extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
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extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
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extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
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extern int N2H_TX_DONE(int* base);
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extern void N2H_CLEAR_IRQ(int chan, int* base);
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extern int N2H_GET_IRQ_CHAN(int* base);
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#endif

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