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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [scr_cpu0/] [tut_n2h_regs.c] - Blame information for rev 145

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1 145 lanttu
#include "tut_n2h_regs.h"
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#include "N2H_registers_and_macros.h"
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#if defined(API)
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struct Channel_reservation {
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    int mem_addr;
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    int amount;
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};
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static struct Channel_reservation
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    channel_reservations[N2H_NUMBER_OF_CHANNELS] = {};
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// Common interrupt service routine. Clear IRQ and call N2H_RX_DONE.
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void isr() {
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    int chan = N2H_GET_IRQ_CHAN(N2H_REGISTERS_BASE_ADDRESS);
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    N2H_RX_DONE( chan, channel_reservations[chan].mem_addr, channel_reservations[chan].amount );
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    channel_reservations[chan].mem_addr = 0;
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    channel_reservations[chan].amount = 0;
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    N2H_RX_CLEAR_IRQ(chan,N2H_REGISTERS_BASE_ADDRESS);
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}
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// eCos specific interrupt handling
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#if defined(ECOS)
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#include <cyg/kernel/kapi.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/hal_cache.h>
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static cyg_interrupt l_rxIrq;
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static cyg_handle_t l_rxIrqHandle;
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extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_handle);
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cyg_uint32 RxIrqIsr(cyg_vector_t vector, cyg_addrword_t data) {
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    cyg_interrupt_mask(vector);
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    cyg_interrupt_post_dsr(l_rxIrqHandle);
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    return (CYG_ISR_HANDLED);
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}
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void RxIrqDsr(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data) {
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    isr();
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    cyg_interrupt_unmask(vector);
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}
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// NIOSII specific interrupt handling
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#else
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void n2h_isr( void* context, int id ) {
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    isr();
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}
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#endif
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void N2H_INIT_ISR() {
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// eCos specific interrupt init    
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#if defined(ECOS)
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    cyg_interrupt_create(
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                         N2H_RX_IRQ,
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                         N2H_RX_IRQ_PRI,
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                         0,
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                         &RxIrqIsr,
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                         &RxIrqDsr,
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                         &l_rxIrqHandle,
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                         &l_rxIrq);
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    cyg_interrupt_attach(l_rxIrqHandle);
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    cyg_interrupt_unmask(N2H_RX_IRQ);
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    N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
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// NIOSII specific interrupt init
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#else
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    alt_irq_register( N2H_RX_IRQ, 0, n2h_isr );
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    N2H_RX_IRQ_ENA( N2H_REGISTERS_BASE_ADDRESS );
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#endif
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}
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void N2H_GET_RX_BUFFER( int* dst, int src, int amount ) {
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    // TODO: check that src is inside RX buffer
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    // TODO: if src and dst are same, do nothing    
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    int i;
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    for( i = 0; i < amount; ++i ) {
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        *(dst + i) = *((int*)src + i);
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    }
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}
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void N2H_PUT_TX_BUFFER( int dst, int* src, int amount ) {
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    // TODO: check that dst is inside TX buffer
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    // TODO: if src and dst are same, do nothing   
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    int i;
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    for( i = 0; i < amount; ++i ) {
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        *((int*)dst + i) = *(src + i);
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    }
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}
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#endif // API
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/*
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* DMA engine configuration functions (Updated on 27/04/2005)
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*/
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// Prepare channel for receiving data.
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void N2H_CHAN_CONF(int channel, int dst_mem_addr, int rx_haddr, int amount,
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                   int* base)
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{
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#ifdef API
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  channel_reservations[channel].mem_addr = dst_mem_addr;
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  channel_reservations[channel].amount = amount;
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#endif
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  N2H_CHAN_MEM_ADDR(channel, dst_mem_addr, base);
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  N2H_CHAN_HIBI_ADDR(channel, rx_haddr, base);
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  N2H_CHAN_AMOUNT(channel, amount, base);
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  N2H_CHAN_INIT(channel, base);
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}
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void N2H_SEND(int src_mem_addr, int amount, int dst_haddr, int* base) {
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  while( !N2H_TX_DONE(base) );
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  N2H_TX_MEM_ADDR(src_mem_addr, base);
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  N2H_TX_AMOUNT(amount, base);
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  N2H_TX_HIBI_ADDR(dst_haddr, base);
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  N2H_TX_COMM_WRITE(base);
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  N2H_TX_START(base);
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}
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// Parameter types were uint32. Int works in other places, so why not here?
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void N2H_SEND_READ(int mem_addr, int amount, int haddr, int* base) {
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  while( !N2H_TX_DONE(base) );
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  N2H_TX_MEM_ADDR(mem_addr, base);
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  N2H_TX_AMOUNT(amount, base);
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  N2H_TX_HIBI_ADDR(haddr, base);
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  N2H_TX_COMM_READ(base);
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  N2H_TX_START(base);
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}
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void N2H_SEND_MSG(int src_mem_addr, int amount, int dst_haddr, int* base) {
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  while( !N2H_TX_DONE(base) );
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  N2H_TX_MEM_ADDR(src_mem_addr, base);
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  N2H_TX_AMOUNT(amount, base);
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  N2H_TX_HIBI_ADDR(dst_haddr, base);
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  N2H_TX_COMM_WRITE_MSG(base);
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  N2H_TX_START(base);
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}
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// Return 0 if transmission is not done yet, 1 otherwise.
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int N2H_TX_DONE(int* base) {
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  int y = 0;
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  N2H_GET_TX_DONE(y, base);
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  return y;
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}
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void N2H_CLEAR_IRQ(int chan, int* base) {
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  N2H_RX_CLEAR_IRQ(chan, base);
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}
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// Returns first channel number which has IRQ flag up.
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// If no interrupts have been received -1 is returned.
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int N2H_GET_IRQ_CHAN(int* base)
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{
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  volatile int * apu = base + 7;
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  int irq_reg = *apu;
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  int mask = 1;
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  int shift = 0;
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  for (shift = 0; shift < 32; shift++) {
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    if ((irq_reg & (mask << shift)) != 0) {
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      return shift;
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    }
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  }
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  return -1;
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}
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