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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [scr_cpu0/] [tut_n2h_regs.h] - Blame information for rev 145

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/*
* History:
*    10/08/2005 by ollil
*        + Copied minor modifications implemented by Ari.
*          This fixed a crash bug in DCT HW based system
*    03/10/2008 by tapiok
*       fixed N2H_RX_IRQ_DIS
*    08/2009 kojo2
*       Added following functions: N2H_INIT_ISR, N2H_RX_DONE,
*                                  N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER
*/
#ifndef __tut_n2h_regs_h_
#define __tut_n2h_regs_h_
 
#ifdef NIOS_II
#include "io.h"
 
#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)
#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)
#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)
#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))
#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 | (IORD(base,4))))
#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))
#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)
#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)
#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)
#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)
#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)
#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)
#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)
#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)
#define N2H_TX_COMM_READ(base) IOWR(base,10,4)
#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)
#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)
#define N2H_TX_START(base) IOWR(base, 4, (0x1 | (IORD(base,4))))
#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)
#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))
#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))
 
 
#else 
 
#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base)       \
  {                                             \
    volatile int * apu = (int*)base;            \
    apu = apu + ((chan) << 4) + 1;              \
    *apu=hibi_addr;                             \
  }
 
#define N2H_CHAN_MEM_ADDR(chan, addr, base)     \
  {                                             \
    volatile int * apu = (int*)base;            \
    apu = apu + ((chan) << 4);                  \
    *apu=addr;                                  \
  }
 
#define N2H_CHAN_AMOUNT(chan, amount, base)     \
  {                                             \
    volatile int * apu = (int*)base;            \
    apu = apu + ((chan) << 4) + 2;              \
    *apu=amount;                                \
  }
 
#define N2H_CHAN_INIT(chan, base)               \
  {                                             \
    volatile int * apu = (int*)base + 5;        \
    *apu=1 << (chan);                           \
  }
 
#define N2H_RX_IRQ_ENA(base)                    \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    *apu= *apu | 0x2;                           \
  }
 
#define N2H_RX_IRQ_DIS(base)                    \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    *apu= *apu & 0xfffffffd;                    \
  }
 
#define N2H_GET_STAT_REG(var, base)             \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    var = *apu >> 16;                           \
  }
 
#define N2H_GET_CONF_REG(var, base)             \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    var = *apu & 0x0000ffff;                    \
  }
 
#define N2H_GET_INIT_REG(var, base)             \
  {                                             \
    volatile int * apu = (int*)base + 5;        \
    var = *apu;                                 \
  }
 
#define N2H_GET_IRQ_REG(var, base)              \
  {                                             \
    volatile int * apu = (int*)base + 7;        \
    var = *apu;                                 \
  }
 
#define N2H_GET_CURR_PTR(var, chan, base)       \
  {                                             \
    volatile int * apu = (int*)base + 3;        \
    apu = apu + ((chan) << 4);                  \
    var = *apu;                                 \
  }
 
#define N2H_TX_MEM_ADDR(addr, base)             \
  {                                             \
    volatile int * apu = (int*)base + 8;        \
    *apu = addr;                                \
  }
 
#define N2H_TX_AMOUNT(amount, base)             \
  {                                             \
    volatile int * apu = (int*)base + 9;        \
    *apu = amount;                              \
  }
 
#define N2H_TX_HIBI_ADDR(haddr, base)           \
  {                                             \
    volatile int * apu = (int*)base + 11;       \
    *apu = haddr;                               \
  }
 
#define N2H_TX_COMM(comm, base)                 \
  {                                             \
    volatile int * apu = (int*)base +10;        \
    *apu = comm;                                \
  }
 
#define N2H_TX_COMM_WRITE(base)                 \
  {                                             \
    volatile int * apu = (int*)base + 10;       \
    *apu = 2;                                   \
  }
 
#define N2H_TX_COMM_READ(base)                  \
  {                                             \
    volatile int * apu = (int*)base + 10;       \
    *apu = 4;                                   \
  }
 
#define N2H_TX_COMM_WRITE_MSG(base)             \
  {                                             \
    volatile int * apu = (int*)base + 10;       \
    *apu = 3;                                   \
  }
 
#define N2H_TX_START(base)                      \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    *apu = *apu | 0x1;                          \
    *apu = *apu & 0xfffffffe;                   \
  }
#define N2H_GET_TX_DONE(y, base)                \
  {                                             \
    volatile int * apu = (int*)base + 4;        \
    y = *apu >> 16;                             \
    y = y & 0x1;                                \
  }
 
#define N2H_RX_CLEAR_IRQ(chan, base)            \
  {                                             \
    volatile int * apu = (int*)base + 7;        \
    *apu = 1 << (chan);                         \
  }
 
 
 
#endif
 
 
#ifdef API
extern void N2H_INIT_ISR();
extern void N2H_RX_DONE( int chan, int mem_addr, int amount );
extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );
extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );
#endif
 
 
/*
* DMA engine configuration
*/
 
extern void N2H_CHAN_CONF( int channel,
                           int mem_addr,
                           int rx_addr,
                           int amount,
                           int* base );
 
extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);
 
extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);
 
extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);
 
extern int N2H_TX_DONE(int* base);
 
extern void N2H_CLEAR_IRQ(int chan, int* base);
 
extern int N2H_GET_IRQ_CHAN(int* base);
 
#endif

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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [scr_cpu0/] [tut_n2h_regs.h] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu	`/*`
2			`* History:`
3			`* 10/08/2005 by ollil`
4			`* + Copied minor modifications implemented by Ari.`
5			`* This fixed a crash bug in DCT HW based system`
6			`* 03/10/2008 by tapiok`
7			`* fixed N2H_RX_IRQ_DIS`
8			`* 08/2009 kojo2`
9			`* Added following functions: N2H_INIT_ISR, N2H_RX_DONE,`
10			`* N2H_PUT_TX_BUFFER, N2H_GET_RX_BUFFER`
11			`*/`
12			`#ifndef __tut_n2h_regs_h_`
13			`#define __tut_n2h_regs_h_`
14
15			`#ifdef NIOS_II`
16			`#include "io.h"`
17
18			`#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) IOWR(base, ((chan) << 4) + 1, hibi_addr)`
19			`#define N2H_CHAN_MEM_ADDR(chan, addr, base) IOWR(base, ((chan) << 4), addr)`
20			`#define N2H_CHAN_AMOUNT(chan, amount, base) IOWR(base, ((chan) << 4) + 2, amount)`
21			`#define N2H_CHAN_INIT(chan, base) IOWR(base, 5 , 1 << (chan))`
22			`#define N2H_RX_IRQ_ENA(base) IOWR(base, 4, (2 \| (IORD(base,4))))`
23			`#define N2H_RX_IRQ_DIS(base) IOWR(base, 4, (0xfffffffd & (IORD(base,4))))`
24			`#define N2H_GET_STAT_REG(var, base) var = (IORD(base, 4) >> 16)`
25			`#define N2H_GET_CONF_REG(var, base) var = (IORD(base, 4) & 0x0000ffff)`
26			`#define N2H_GET_INIT_REG(var, base) var = IORD(base, 5)`
27			`#define N2H_GET_IRQ_REG(var, base) var = IORD(base, 7)`
28			`#define N2H_TX_MEM_ADDR(addr, base) IOWR(base, 8, addr)`
29			`#define N2H_TX_AMOUNT(amount, base) IOWR(base, 9, amount)`
30			`#define N2H_TX_COMM(comm, base) IOWR(base,10,comm)`
31			`#define N2H_TX_COMM_WRITE(base) IOWR(base,10,2)`
32			`#define N2H_TX_COMM_READ(base) IOWR(base,10,4)`
33			`#define N2H_TX_COMM_WRITE_MSG(base) IOWR(base,10,3)`
34			`#define N2H_TX_HIBI_ADDR(addr, base) IOWR(base, 11, addr)`
35			`#define N2H_TX_START(base) IOWR(base, 4, (0x1 \| (IORD(base,4))))`
36			`#define N2H_GET_TX_DONE(var, base) var = ((IORD(base, 4) >> 16) & 0x1)`
37			`#define N2H_GET_CURR_PTR(var, chan, base) var = (IORD(base,((chan) << 4) + 3))`
38			`#define N2H_RX_CLEAR_IRQ(chan, base) IOWR(base, 7, (1 << (chan)))`
39
40
41			`#else`
42
43			`#define N2H_CHAN_HIBI_ADDR(chan, hibi_addr, base) \`
44			`{ \`
45			`volatile int * apu = (int*)base; \`
46			`apu = apu + ((chan) << 4) + 1; \`
47			`*apu=hibi_addr; \`
48			`}`
49
50			`#define N2H_CHAN_MEM_ADDR(chan, addr, base) \`
51			`{ \`
52			`volatile int * apu = (int*)base; \`
53			`apu = apu + ((chan) << 4); \`
54			`*apu=addr; \`
55			`}`
56
57			`#define N2H_CHAN_AMOUNT(chan, amount, base) \`
58			`{ \`
59			`volatile int * apu = (int*)base; \`
60			`apu = apu + ((chan) << 4) + 2; \`
61			`*apu=amount; \`
62			`}`
63
64			`#define N2H_CHAN_INIT(chan, base) \`
65			`{ \`
66			`volatile int * apu = (int*)base + 5; \`
67			`*apu=1 << (chan); \`
68			`}`
69
70			`#define N2H_RX_IRQ_ENA(base) \`
71			`{ \`
72			`volatile int * apu = (int*)base + 4; \`
73			`apu= apu \| 0x2; \`
74			`}`
75
76			`#define N2H_RX_IRQ_DIS(base) \`
77			`{ \`
78			`volatile int * apu = (int*)base + 4; \`
79			`apu= apu & 0xfffffffd; \`
80			`}`
81
82			`#define N2H_GET_STAT_REG(var, base) \`
83			`{ \`
84			`volatile int * apu = (int*)base + 4; \`
85			`var = *apu >> 16; \`
86			`}`
87
88			`#define N2H_GET_CONF_REG(var, base) \`
89			`{ \`
90			`volatile int * apu = (int*)base + 4; \`
91			`var = *apu & 0x0000ffff; \`
92			`}`
93
94			`#define N2H_GET_INIT_REG(var, base) \`
95			`{ \`
96			`volatile int * apu = (int*)base + 5; \`
97			`var = *apu; \`
98			`}`
99
100			`#define N2H_GET_IRQ_REG(var, base) \`
101			`{ \`
102			`volatile int * apu = (int*)base + 7; \`
103			`var = *apu; \`
104			`}`
105
106			`#define N2H_GET_CURR_PTR(var, chan, base) \`
107			`{ \`
108			`volatile int * apu = (int*)base + 3; \`
109			`apu = apu + ((chan) << 4); \`
110			`var = *apu; \`
111			`}`
112
113			`#define N2H_TX_MEM_ADDR(addr, base) \`
114			`{ \`
115			`volatile int * apu = (int*)base + 8; \`
116			`*apu = addr; \`
117			`}`
118
119			`#define N2H_TX_AMOUNT(amount, base) \`
120			`{ \`
121			`volatile int * apu = (int*)base + 9; \`
122			`*apu = amount; \`
123			`}`
124
125			`#define N2H_TX_HIBI_ADDR(haddr, base) \`
126			`{ \`
127			`volatile int * apu = (int*)base + 11; \`
128			`*apu = haddr; \`
129			`}`
130
131			`#define N2H_TX_COMM(comm, base) \`
132			`{ \`
133			`volatile int * apu = (int*)base +10; \`
134			`*apu = comm; \`
135			`}`
136
137			`#define N2H_TX_COMM_WRITE(base) \`
138			`{ \`
139			`volatile int * apu = (int*)base + 10; \`
140			`*apu = 2; \`
141			`}`
142
143			`#define N2H_TX_COMM_READ(base) \`
144			`{ \`
145			`volatile int * apu = (int*)base + 10; \`
146			`*apu = 4; \`
147			`}`
148
149			`#define N2H_TX_COMM_WRITE_MSG(base) \`
150			`{ \`
151			`volatile int * apu = (int*)base + 10; \`
152			`*apu = 3; \`
153			`}`
154
155			`#define N2H_TX_START(base) \`
156			`{ \`
157			`volatile int * apu = (int*)base + 4; \`
158			`apu = apu \| 0x1; \`
159			`apu = apu & 0xfffffffe; \`
160			`}`
161			`#define N2H_GET_TX_DONE(y, base) \`
162			`{ \`
163			`volatile int * apu = (int*)base + 4; \`
164			`y = *apu >> 16; \`
165			`y = y & 0x1; \`
166			`}`
167
168			`#define N2H_RX_CLEAR_IRQ(chan, base) \`
169			`{ \`
170			`volatile int * apu = (int*)base + 7; \`
171			`*apu = 1 << (chan); \`
172			`}`
173
174
175
176			`#endif`
177
178
179			`#ifdef API`
180			`extern void N2H_INIT_ISR();`
181			`extern void N2H_RX_DONE( int chan, int mem_addr, int amount );`
182			`extern void N2H_GET_RX_BUFFER( int* dst, int src, int amount );`
183			`extern void N2H_PUT_TX_BUFFER( int dst, int* src, int amount );`
184			`#endif`
185
186
187			`/*`
188			`* DMA engine configuration`
189			`*/`
190
191			`extern void N2H_CHAN_CONF( int channel,`
192			`int mem_addr,`
193			`int rx_addr,`
194			`int amount,`
195			`int* base );`
196
197			`extern void N2H_SEND(int mem_addr, int amount, int haddr, int* base);`
198
199			`extern void N2H_READ(int mem_addr, int amount, int haddr, int* base);`
200
201			`extern void N2H_SEND_MSG(int mem_addr, int amount, int haddr, int* base);`
202
203			`extern int N2H_TX_DONE(int* base);`
204
205			`extern void N2H_CLEAR_IRQ(int chan, int* base);`
206
207			`extern int N2H_GET_IRQ_CHAN(int* base);`
208
209			`#endif`