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https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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// *****************************************************************************
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// File : N2H_registers_and_macros.h
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// Author : Tero Arpinen
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// Date : 22.12.2004
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// Decription : This file contains customizable register address
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// definitions
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// for N2H interface and some needed macros
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//
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// Version history : 22.12.2004 tar Original version
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// : 06.07.2005 tar Modified to work with N2H2
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// : 02.10.2009 tko Removed unneeded macros
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// *****************************************************************************
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#ifndef N2H_REGISTERS_AND_MACROS_H
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#define N2H_REGISTERS_AND_MACROS_H
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// DEFINE FOLLOWING REGISTERS ACCORDING TO NIOS OR NIOS II HARDWARE
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// CONFIGURATION
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// N2H2 Avalon slave base address
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#define N2H_REGISTERS_BASE_ADDRESS ((void*) N2H2_CHAN_1_BASE)
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// Buffer start address in cpu's memory
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#define N2H_REGISTERS_BUFFER_START (SHARED_MEM_1_BASE)
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// Writeable registers
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// set bit 31 to 1 so that writes and reads bypass cache
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#define N2H_REGISTERS_TX_BUFFER_START (0x80000000 | SHARED_MEM_1_BASE)
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#define N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH (0x00000400)
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#define N2H_REGISTERS_TX_BUFFER_END (N2H_REGISTERS_TX_BUFFER_START + \
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N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH - 1)
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// Readable registers
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#define N2H_REGISTERS_RX_BUFFER_START (N2H_REGISTERS_TX_BUFFER_START + N2H_REGISTERS_TX_BUFFER_BYTE_LENGTH)
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#define N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH (0x00000C00)
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#define N2H_REGISTERS_RX_BUFFER_END (N2H_REGISTERS_RX_BUFFER_START + \
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N2H_REGISTERS_RX_BUFFER_BYTE_LENGTH \
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- 1)
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// N2H Interrupt registers, numbers and priorities
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#define N2H_RX_IRQ (2)
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#define N2H_RX_IRQ_PRI (3)
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// N2H Channels
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#define N2H_NUMBER_OF_CHANNELS (8)
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#endif // N2H_REGISTERS_AND_MACROS_H
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