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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [support/] [basic_waves.do] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu 
onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider Top
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add wave -noupdate -format Logic /test_bench/clk_0
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add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_0
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add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_1
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add wave -noupdate -format Logic /test_bench/cpu_resetrequest_to_the_cpu_2
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add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_0
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add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_1
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add wave -noupdate -format Logic /test_bench/cpu_resettaken_from_the_cpu_2
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add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_0
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add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_1
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add wave -noupdate -color Tan -format Logic /test_bench/hibi_av_in_to_the_n2h2_chan_2
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add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_0
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add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_1
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add wave -noupdate -color Gold -format Logic /test_bench/hibi_av_out_from_the_n2h2_chan_2
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add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_0
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add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_1
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add wave -noupdate -format Literal /test_bench/hibi_comm_in_to_the_n2h2_chan_2
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add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_0
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add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_1
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add wave -noupdate -format Literal /test_bench/hibi_comm_out_from_the_n2h2_chan_2
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_0
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_1
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_in_to_the_n2h2_chan_2
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_0
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_1
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibi_data_out_from_the_n2h2_chan_2
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add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_0
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add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_1
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add wave -noupdate -format Logic /test_bench/hibi_empty_in_to_the_n2h2_chan_2
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add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_0
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add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_1
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add wave -noupdate -color Orchid -format Logic /test_bench/hibi_full_in_to_the_n2h2_chan_2
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add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_0
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add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_1
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add wave -noupdate -format Logic /test_bench/hibi_re_out_from_the_n2h2_chan_2
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add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_0
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add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_1
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add wave -noupdate -color Plum -format Logic /test_bench/hibi_we_out_from_the_n2h2_chan_2
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add wave -noupdate -format Logic /test_bench/reset_n
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add wave -noupdate -format Literal /test_bench/comm_from_n
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/data_from_n
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add wave -noupdate -format Literal /test_bench/av_from_n
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add wave -noupdate -format Literal /test_bench/we_from_n
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add wave -noupdate -format Literal /test_bench/re_from_n
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add wave -noupdate -format Literal /test_bench/comm_to_n
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/data_to_n
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add wave -noupdate -format Literal /test_bench/av_to_n
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add wave -noupdate -format Literal /test_bench/full_to_n
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add wave -noupdate -format Literal /test_bench/one_p_to_n
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add wave -noupdate -format Literal /test_bench/empty_to_n
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add wave -noupdate -format Literal /test_bench/one_d_to_n
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add wave -noupdate -divider Hibi_0
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/rst_n
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_comm_in
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_data_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_full_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_lock_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_av_in
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_comm_in
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_data_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_av_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_we_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_re_in
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_comm_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_data_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_full_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_lock_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/bus_av_out
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_comm_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_data_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_av_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_full_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_one_p_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_empty_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/agent_one_d_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_dw_h
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/we_0_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/we_1_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/full_0_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/full_1_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_p_0_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_p_1_h_dw
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_0_h_mr
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_0_h_mr
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/data_1_h_mr
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/comm_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_0_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/av_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/re_0_mr_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/re_1_mr_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/empty_0_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/empty_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_d_0_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__0/wrapper/one_d_1_h_mr
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add wave -noupdate -divider Hibi_1
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/rst_n
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_comm_in
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_data_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_full_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_lock_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_av_in
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_comm_in
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_data_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_av_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_we_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_re_in
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_comm_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_data_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_full_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_lock_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/bus_av_out
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_comm_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_data_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_av_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_full_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_one_p_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_empty_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/agent_one_d_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_dw_h
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/we_0_dw_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/full_0_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/full_1_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_p_0_h_dw
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_p_1_h_dw
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_0_h_mr
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_0_h_mr
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/data_1_h_mr
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/comm_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_0_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/av_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/re_0_mr_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/re_1_mr_h
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/empty_1_h_mr
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__1/wrapper/one_d_0_h_mr
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add wave -noupdate -divider Hibi_2
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_sync_clk
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/rst_n
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_comm_in
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_data_in
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_re_in
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add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_comm_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/bus_data_out
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add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/agent_data_out
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add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/we_1_dw_h
185 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/full_0_h_dw
186 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/full_1_h_dw
187 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_p_0_h_dw
188 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_p_1_h_dw
189 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/data_0_h_mr
190 
add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/comm_0_h_mr
191 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/data_1_h_mr
192 
add wave -noupdate -format Literal /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/comm_1_h_mr
193 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/av_0_h_mr
194 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/av_1_h_mr
195 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/re_0_mr_h
196 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/re_1_mr_h
197 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/empty_0_h_mr
198 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/empty_1_h_mr
199 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_d_0_h_mr
200 
add wave -noupdate -format Logic /test_bench/hibiv3_r4_1/segments__0/wrappers__2/wrapper/one_d_1_h_mr
201 
add wave -noupdate -divider N2H2_0
202 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_cfg
203 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_tx
204 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/clk_rx
205 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/rst_n
206 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_addr_out_rx
207 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_we_out_rx
208 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_be_out_rx
209 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_writedata_out_rx
210 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_waitrequest_in_rx
211 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_addr_in
212 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_writedata_in
213 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_we_in
214 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_readdata_out
215 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_re_in
216 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_cs_in
217 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_cfg_waitrequest_out
218 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_addr_out_tx
219 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_re_out_tx
220 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_readdata_in_tx
221 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_waitrequest_in_tx
222 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/avalon_readdatavalid_in_tx
223 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_data_in
224 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_av_in
225 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_empty_in
226 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_comm_in
227 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_re_out
228 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_data_out
229 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_av_out
230 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_full_in
231 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_comm_out
232 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/hibi_we_out
233 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/rx_irq_out
234 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_start_from_rx
235 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_comm_from_rx
236 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_mem_addr_from_rx
237 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_hibi_addr_from_rx
238 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_amount_from_rx
239 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/tx_status_done_to_rx
240 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/real_rst_n
241 
add wave -noupdate -divider {n2h2_0 channels}
242 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/clk
243 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/rst_n
244 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_out
245 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_we_out
246 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_out
247 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_writedata_out
248 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_waitrequest_in
249 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_data_in
250 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_av_in
251 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_empty_in
252 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_comm_in
253 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_re_out
254 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_addr_in
255 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_writedata_in
256 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_we_in
257 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_readdata_out
258 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_re_in
259 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_cs_in
260 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
261 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/rx_irq_out
262 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_start_out
263 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_comm_out
264 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_mem_addr_out
265 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_hibi_addr_out
266 
add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_amount_out
267 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_status_done_in
268 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/mem_addr_r
269 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/sender_addr_r
270 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_amount_r
271 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/control_r
272 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_mem_addr_r
273 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_hibi_addr_r
274 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_amount_r
275 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_comm_r
276 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/init_chan_r
277 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_chan_r
278 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/current_mem_addr_r
279 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/current_be_r
280 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_r
281 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/status_r
282 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_reset_r
283 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/hibi_re_r
284 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_we_r
285 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx
286 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx_irq_r
287 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/unknown_rx_r
288 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_illegal
289 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/tx_illegal_r
290 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/ignore_tx_write
291 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/ignored_last_tx_r
292 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_r
293 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/curr_chan_avalon_we_r
294 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_wes
295 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/matches
296 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/matches_cmb
297 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/irq_ack_r
298 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_addr_temp
299 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_be_temp
300 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
301 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
302 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_write
303 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_reg
304 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_rx_chan_1/cfg_tx_reg_used
305 
add wave -noupdate -divider {n2h_0 tx}
306 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/clk
307 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/rst_n
308 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_addr_out
309 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_re_out
310 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_readdata_in
311 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_waitrequest_in
312 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_readdatavalid_in
313 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_data_out
314 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_av_out
315 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_full_in
316 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_comm_out
317 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_we_out
318 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_start_in
319 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_status_done_out
320 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_comm_in
321 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_hibi_addr_in
322 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_ram_addr_in
323 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/tx_amount_in
324 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/control_r
325 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_en_r
326 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_value_r
327 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_cnt_load_r
328 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_r
329 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_en_r
330 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_value_r
331 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_cnt_load_r
332 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/amount_r
333 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_amount_eq
334 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/addr_to_stop_r
335 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/avalon_re_r
336 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/start_re_r
337 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_write_addr_r
338 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/data_src_sel
339 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_we_r
340 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_0/n2h2_chan_0/n2h2_tx_1/hibi_stop_we_r
341 
add wave -noupdate -divider N2H2_1
342 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_addr_in
343 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_we_in
344 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_re_in
345 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_cfg_cs_in
346 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_writedata_in
347 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_cfg_readdata_out
348 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/avalon_cfg_waitrequest_out
349 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/hibi_data_in
350 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_av_in
351 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_empty_in
352 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/hibi_comm_in
353 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_re_out
354 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/hibi_data_out
355 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_av_out
356 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_full_in
357 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/hibi_comm_out
358 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/hibi_we_out
359 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_cfg
360 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/rst_n
361 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_tx
362 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/clk_rx
363 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/rx_irq_out
364 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_addr_out_rx
365 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_we_out_rx
366 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/avalon_be_out_rx
367 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_writedata_out_rx
368 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_waitrequest_in_rx
369 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_readdatavalid_in_tx
370 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_waitrequest_in_tx
371 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_readdata_in_tx
372 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/avalon_re_out_tx
373 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/avalon_addr_out_tx
374 
add wave -noupdate -divider {n2h_1 channels}
375 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/clk
376 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/rst_n
377 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_out
378 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_we_out
379 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_out
380 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_writedata_out
381 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_waitrequest_in
382 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_data_in
383 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_av_in
384 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_empty_in
385 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_comm_in
386 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_re_out
387 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_addr_in
388 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_writedata_in
389 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_we_in
390 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_readdata_out
391 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_re_in
392 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_cs_in
393 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
394 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/rx_irq_out
395 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_start_out
396 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_comm_out
397 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_mem_addr_out
398 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_hibi_addr_out
399 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_amount_out
400 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_status_done_in
401 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/mem_addr_r
402 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/sender_addr_r
403 
add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_amount_r
404 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/control_r
405 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_mem_addr_r
406 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_hibi_addr_r
407 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_amount_r
408 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_comm_r
409 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/init_chan_r
410 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_chan_r
411 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/current_mem_addr_r
412 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/current_be_r
413 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_r
414 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/status_r
415 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_reset_r
416 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/hibi_re_r
417 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_we_r
418 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx
419 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx_irq_r
420 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/unknown_rx_r
421 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_illegal
422 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/tx_illegal_r
423 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/ignore_tx_write
424 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/ignored_last_tx_r
425 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_r
426 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/curr_chan_avalon_we_r
427 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_wes
428 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/matches
429 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/matches_cmb
430 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/irq_ack_r
431 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_addr_temp
432 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_be_temp
433 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
434 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
435 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_write
436 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_reg
437 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_rx_chan_1/cfg_tx_reg_used
438 
add wave -noupdate -divider {n2h_1 tx}
439 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/clk
440 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/rst_n
441 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_addr_out
442 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_re_out
443 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_readdata_in
444 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_waitrequest_in
445 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_readdatavalid_in
446 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_data_out
447 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_av_out
448 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_full_in
449 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_comm_out
450 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_we_out
451 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_start_in
452 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_status_done_out
453 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_comm_in
454 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_hibi_addr_in
455 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_ram_addr_in
456 
add wave -noupdate -format Literal -radix unsigned /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/tx_amount_in
457 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/control_r
458 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_en_r
459 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_value_r
460 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_cnt_load_r
461 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_r
462 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_en_r
463 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_value_r
464 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_cnt_load_r
465 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/amount_r
466 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_amount_eq
467 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/addr_to_stop_r
468 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/avalon_re_r
469 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/start_re_r
470 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_write_addr_r
471 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/data_src_sel
472 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_we_r
473 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_1/n2h2_chan_1/n2h2_tx_1/hibi_stop_we_r
474 
add wave -noupdate -divider N2H2_2
475 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_addr_in
476 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_we_in
477 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_re_in
478 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_cfg_cs_in
479 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_writedata_in
480 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_cfg_readdata_out
481 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/hibi_data_in
482 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_av_in
483 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_empty_in
484 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/hibi_comm_in
485 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_re_out
486 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/hibi_data_out
487 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_av_out
488 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_full_in
489 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/hibi_comm_out
490 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/hibi_we_out
491 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_cfg
492 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/rst_n
493 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_tx
494 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/clk_rx
495 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/rx_irq_out
496 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_addr_out_rx
497 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_we_out_rx
498 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/avalon_be_out_rx
499 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_writedata_out_rx
500 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_waitrequest_in_rx
501 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_readdatavalid_in_tx
502 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_waitrequest_in_tx
503 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_readdata_in_tx
504 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/avalon_re_out_tx
505 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/avalon_addr_out_tx
506 
add wave -noupdate -divider {n2h_2 channels}
507 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/clk
508 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/rst_n
509 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_out
510 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_we_out
511 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_out
512 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_writedata_out
513 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_waitrequest_in
514 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_data_in
515 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_av_in
516 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_empty_in
517 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_comm_in
518 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_re_out
519 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_addr_in
520 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_writedata_in
521 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_we_in
522 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_readdata_out
523 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_re_in
524 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_cs_in
525 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out
526 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/rx_irq_out
527 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_start_out
528 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_comm_out
529 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_mem_addr_out
530 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_hibi_addr_out
531 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_amount_out
532 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_status_done_in
533 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/mem_addr_r
534 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/sender_addr_r
535 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_amount_r
536 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/control_r
537 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_mem_addr_r
538 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_hibi_addr_r
539 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_amount_r
540 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_comm_r
541 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/init_chan_r
542 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_chan_r
543 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/current_mem_addr_r
544 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/current_be_r
545 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_r
546 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/status_r
547 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_reset_r
548 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/hibi_re_r
549 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_we_r
550 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx
551 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx_irq_r
552 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/unknown_rx_r
553 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_illegal
554 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/tx_illegal_r
555 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/ignore_tx_write
556 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/ignored_last_tx_r
557 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_r
558 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/curr_chan_avalon_we_r
559 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_wes
560 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/matches
561 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/matches_cmb
562 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/irq_ack_r
563 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_addr_temp
564 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_be_temp
565 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_r
566 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/avalon_cfg_waitrequest_out_s
567 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_write
568 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_reg
569 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_rx_chan_1/cfg_tx_reg_used
570 
add wave -noupdate -divider {n2h_2 tx}
571 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/clk
572 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/rst_n
573 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_addr_out
574 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_re_out
575 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_readdata_in
576 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_waitrequest_in
577 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_readdatavalid_in
578 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_data_out
579 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_av_out
580 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_full_in
581 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_comm_out
582 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_we_out
583 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_start_in
584 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_status_done_out
585 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_comm_in
586 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_hibi_addr_in
587 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_ram_addr_in
588 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/tx_amount_in
589 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/control_r
590 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_en_r
591 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_value_r
592 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_cnt_load_r
593 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_r
594 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_en_r
595 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_value_r
596 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_cnt_load_r
597 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/amount_r
598 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_amount_eq
599 
add wave -noupdate -format Literal /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/addr_to_stop_r
600 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/avalon_re_r
601 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/start_re_r
602 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_write_addr_r
603 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/data_src_sel
604 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_we_r
605 
add wave -noupdate -format Logic /test_bench/dut/the_n2h2_chan_2/n2h2_chan_2/n2h2_tx_1/hibi_stop_we_r
606 
add wave -noupdate -divider jtag_uart_1
607 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_address
608 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_chipselect
609 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_irq
610 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_read_n
611 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_readdata
612 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_waitrequest
613 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/av_write_n
614 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_1/av_writedata
615 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/dataavailable
616 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_1/readyfordata
617 
add wave -noupdate -divider cpu_2
618 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/i_readdata
619 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_readdatavalid
620 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_waitrequest
621 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/i_address
622 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/i_read
623 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/clk
624 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/reset_n
625 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_readdata
626 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_waitrequest
627 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_address
628 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_byteenable
629 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_read
630 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_write
631 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_writedata
632 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/d_irq
633 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/d_readdatavalid
634 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/cpu_resetrequest
635 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/cpu_resettaken
636 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_pcb
637 
add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_vinst
638 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_valid
639 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_2/the_cpu_2_test_bench/w_iw
640 
add wave -noupdate -divider onchip_memory2_1
641 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_1/chipselect
642 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_1/write
643 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/address
644 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_1/byteenable
645 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/readdata
646 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_1/writedata
647 
add wave -noupdate -divider cpu_0
648 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/i_readdata
649 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_readdatavalid
650 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_waitrequest
651 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/i_address
652 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/i_read
653 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/clk
654 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/reset_n
655 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_readdata
656 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_waitrequest
657 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_address
658 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_byteenable
659 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_read
660 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_write
661 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_writedata
662 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/d_irq
663 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/d_readdatavalid
664 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/cpu_resetrequest
665 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/cpu_resettaken
666 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_pcb
667 
add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_vinst
668 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_valid
669 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_0/the_cpu_0_test_bench/w_iw
670 
add wave -noupdate -divider jtag_uart_0
671 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_address
672 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_chipselect
673 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_irq
674 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_read_n
675 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_readdata
676 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_waitrequest
677 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/av_write_n
678 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_0/av_writedata
679 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/dataavailable
680 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_0/readyfordata
681 
add wave -noupdate -divider onchip_memory2_0
682 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_0/chipselect
683 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_0/write
684 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/address
685 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_0/byteenable
686 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/readdata
687 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_0/writedata
688 
add wave -noupdate -divider shared_mem_0
689 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/chipselect
690 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/write
691 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/address
692 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_0/byteenable
693 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/readdata
694 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/writedata
695 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/chipselect2
696 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_0/write2
697 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/address2
698 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_0/byteenable2
699 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/readdata2
700 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_0/writedata2
701 
add wave -noupdate -divider cpu_1
702 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/i_readdata
703 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_readdatavalid
704 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_waitrequest
705 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/i_address
706 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/i_read
707 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/clk
708 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/reset_n
709 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_readdata
710 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_waitrequest
711 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_address
712 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_byteenable
713 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_read
714 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_write
715 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_writedata
716 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/d_irq
717 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/d_readdatavalid
718 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/cpu_resetrequest
719 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/cpu_resettaken
720 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_pcb
721 
add wave -noupdate -format Literal -radix ascii /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_vinst
722 
add wave -noupdate -format Logic -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_valid
723 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_cpu_1/the_cpu_1_test_bench/w_iw
724 
add wave -noupdate -divider jtag_uart_2
725 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_address
726 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_chipselect
727 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_irq
728 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_read_n
729 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_readdata
730 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_waitrequest
731 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/av_write_n
732 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_jtag_uart_2/av_writedata
733 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/dataavailable
734 
add wave -noupdate -format Logic /test_bench/dut/the_jtag_uart_2/readyfordata
735 
add wave -noupdate -divider shared_mem_2
736 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/chipselect
737 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/write
738 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/address
739 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_2/byteenable
740 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/readdata
741 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/writedata
742 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/chipselect2
743 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_2/write2
744 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/address2
745 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_2/byteenable2
746 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/readdata2
747 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_2/writedata2
748 
add wave -noupdate -divider shared_mem_1
749 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/chipselect
750 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/write
751 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/address
752 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_1/byteenable
753 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/readdata
754 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/writedata
755 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/chipselect2
756 
add wave -noupdate -format Logic /test_bench/dut/the_shared_mem_1/write2
757 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/address2
758 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_shared_mem_1/byteenable2
759 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/readdata2
760 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_shared_mem_1/writedata2
761 
add wave -noupdate -divider onchip_memory2_2
762 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_2/chipselect
763 
add wave -noupdate -format Logic /test_bench/dut/the_onchip_memory2_2/write
764 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/address
765 
add wave -noupdate -format Literal -radix binary /test_bench/dut/the_onchip_memory2_2/byteenable
766 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/readdata
767 
add wave -noupdate -format Literal -radix hexadecimal /test_bench/dut/the_onchip_memory2_2/writedata
768 
TreeUpdate [SetDefaultTree]
769 
WaveRestoreCursors {{Cursor 1} {29713541667 ps} 0}
770 
configure wave -namecolwidth 240
771 
configure wave -valuecolwidth 168
772 
configure wave -justifyvalue right
773 
configure wave -signalnamewidth 1
774 
configure wave -snapdistance 10
775 
configure wave -datasetprefix 0
776 
configure wave -rowmargin 4
777 
configure wave -childrowmargin 2
778 
configure wave -gridoffset 0
779 
configure wave -gridperiod 1
780 
configure wave -griddelta 40
781 
configure wave -timeline 0
782 
configure wave -timelineunits ms
783 
update
784 
WaveRestoreZoom {0 ps} {105 ms}

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