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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [support/] [hibi_add.vhd] - Blame information for rev 145

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1 145 lanttu
 
2
 
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-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
4
 
5
signal cpu_0_reset : std_logic;
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signal cpu_1_reset : std_logic;
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signal cpu_2_reset : std_logic;
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signal cpu_0_reset_taken : std_logic;
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signal cpu_1_reset_taken : std_logic;
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signal cpu_2_reset_taken : std_logic;
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signal comm_from_n : std_logic_vector(5*3-1 downto 0);
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signal data_from_n : std_logic_vector(32*3-1 downto 0);
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signal av_from_n : std_logic_vector(3-1 downto 0);
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signal we_from_n : std_logic_vector(3-1 downto 0);
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signal re_from_n : std_logic_vector(3-1 downto 0);
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signal comm_to_n : std_logic_vector(5*3-1 downto 0);
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signal data_to_n : std_logic_vector(32*3-1 downto 0);
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signal av_to_n : std_logic_vector(3-1 downto 0);
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signal full_to_n : std_logic_vector(3-1 downto 0);
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signal one_p_to_n : std_logic_vector(3-1 downto 0);
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signal empty_to_n : std_logic_vector(3-1 downto 0);
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signal one_d_to_n : std_logic_vector(3-1 downto 0);
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-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
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begin
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  --
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  -- CHECK DUTS NAME !
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  --
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  --Set us up the Dut
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  DUT : n2h2_s
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    port map(
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      cpu_resettaken_from_the_cpu_0 => cpu_resettaken_from_the_cpu_0,
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      cpu_resettaken_from_the_cpu_1 => cpu_resettaken_from_the_cpu_1,
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      cpu_resettaken_from_the_cpu_2 => cpu_resettaken_from_the_cpu_2,
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      hibi_av_out_from_the_n2h2_chan_0 => hibi_av_out_from_the_n2h2_chan_0,
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      hibi_av_out_from_the_n2h2_chan_1 => hibi_av_out_from_the_n2h2_chan_1,
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      hibi_av_out_from_the_n2h2_chan_2 => hibi_av_out_from_the_n2h2_chan_2,
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      hibi_comm_out_from_the_n2h2_chan_0 => hibi_comm_out_from_the_n2h2_chan_0,
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      hibi_comm_out_from_the_n2h2_chan_1 => hibi_comm_out_from_the_n2h2_chan_1,
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      hibi_comm_out_from_the_n2h2_chan_2 => hibi_comm_out_from_the_n2h2_chan_2,
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      hibi_data_out_from_the_n2h2_chan_0 => hibi_data_out_from_the_n2h2_chan_0,
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      hibi_data_out_from_the_n2h2_chan_1 => hibi_data_out_from_the_n2h2_chan_1,
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      hibi_data_out_from_the_n2h2_chan_2 => hibi_data_out_from_the_n2h2_chan_2,
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      hibi_re_out_from_the_n2h2_chan_0 => hibi_re_out_from_the_n2h2_chan_0,
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      hibi_re_out_from_the_n2h2_chan_1 => hibi_re_out_from_the_n2h2_chan_1,
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      hibi_re_out_from_the_n2h2_chan_2 => hibi_re_out_from_the_n2h2_chan_2,
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      hibi_we_out_from_the_n2h2_chan_0 => hibi_we_out_from_the_n2h2_chan_0,
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      hibi_we_out_from_the_n2h2_chan_1 => hibi_we_out_from_the_n2h2_chan_1,
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      hibi_we_out_from_the_n2h2_chan_2 => hibi_we_out_from_the_n2h2_chan_2,
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      clk_0 => clk_0,
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      cpu_resetrequest_to_the_cpu_0 => cpu_resetrequest_to_the_cpu_0,
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      cpu_resetrequest_to_the_cpu_1 => cpu_resetrequest_to_the_cpu_1,
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      cpu_resetrequest_to_the_cpu_2 => cpu_resetrequest_to_the_cpu_2,
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      hibi_av_in_to_the_n2h2_chan_0 => hibi_av_in_to_the_n2h2_chan_0,
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      hibi_av_in_to_the_n2h2_chan_1 => hibi_av_in_to_the_n2h2_chan_1,
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      hibi_av_in_to_the_n2h2_chan_2 => hibi_av_in_to_the_n2h2_chan_2,
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      hibi_comm_in_to_the_n2h2_chan_0 => hibi_comm_in_to_the_n2h2_chan_0,
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      hibi_comm_in_to_the_n2h2_chan_1 => hibi_comm_in_to_the_n2h2_chan_1,
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      hibi_comm_in_to_the_n2h2_chan_2 => hibi_comm_in_to_the_n2h2_chan_2,
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      hibi_data_in_to_the_n2h2_chan_0 => hibi_data_in_to_the_n2h2_chan_0,
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      hibi_data_in_to_the_n2h2_chan_1 => hibi_data_in_to_the_n2h2_chan_1,
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      hibi_data_in_to_the_n2h2_chan_2 => hibi_data_in_to_the_n2h2_chan_2,
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      hibi_empty_in_to_the_n2h2_chan_0 => hibi_empty_in_to_the_n2h2_chan_0,
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      hibi_empty_in_to_the_n2h2_chan_1 => hibi_empty_in_to_the_n2h2_chan_1,
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      hibi_empty_in_to_the_n2h2_chan_2 => hibi_empty_in_to_the_n2h2_chan_2,
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      hibi_full_in_to_the_n2h2_chan_0 => hibi_full_in_to_the_n2h2_chan_0,
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      hibi_full_in_to_the_n2h2_chan_1 => hibi_full_in_to_the_n2h2_chan_1,
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      hibi_full_in_to_the_n2h2_chan_2 => hibi_full_in_to_the_n2h2_chan_2,
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      reset_n => reset_n
76
    );
77
 
78
 
79
  process
80
  begin
81
    clk_0 <= '0';
82
    loop
83
       wait for 10 ns;
84
       clk_0 <= not clk_0;
85
    end loop;
86
  end process;
87
  PROCESS
88
    BEGIN
89
       reset_n <= '0';
90
       wait for 200 ns;
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       reset_n <= '1';
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    WAIT;
93
  END PROCESS;
94
 
95
 
96
-- <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
97
 
98
  cpu_0_reset_taken <= cpu_resettaken_from_the_cpu_0;
99
  cpu_1_reset_taken <= cpu_resettaken_from_the_cpu_1;
100
  cpu_2_reset_taken <= cpu_resettaken_from_the_cpu_2;
101
 
102
  cpu_resetrequest_to_the_cpu_0 <= cpu_0_reset;
103
  cpu_resetrequest_to_the_cpu_1 <= cpu_1_reset;
104
  cpu_resetrequest_to_the_cpu_2 <= cpu_2_reset;
105
 
106
  av_from_n(0) <= hibi_av_out_from_the_n2h2_chan_0;
107
  av_from_n(1) <= hibi_av_out_from_the_n2h2_chan_1;
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  av_from_n(2) <= hibi_av_out_from_the_n2h2_chan_2;
109
 
110
  comm_from_n(5*1-1 downto 5*0) <= hibi_comm_out_from_the_n2h2_chan_0;
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  comm_from_n(5*2-1 downto 5*1) <= hibi_comm_out_from_the_n2h2_chan_1;
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  comm_from_n(5*3-1 downto 5*2) <= hibi_comm_out_from_the_n2h2_chan_2;
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114
  data_from_n(32*1-1 downto 32*0) <= hibi_data_out_from_the_n2h2_chan_0;
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  data_from_n(32*2-1 downto 32*1) <= hibi_data_out_from_the_n2h2_chan_1;
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  data_from_n(32*3-1 downto 32*2) <= hibi_data_out_from_the_n2h2_chan_2;
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118
  re_from_n(0) <= hibi_re_out_from_the_n2h2_chan_0;
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  re_from_n(1) <= hibi_re_out_from_the_n2h2_chan_1;
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  re_from_n(2) <= hibi_re_out_from_the_n2h2_chan_2;
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122
  we_from_n(0) <= hibi_we_out_from_the_n2h2_chan_0;
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  we_from_n(1) <= hibi_we_out_from_the_n2h2_chan_1;
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  we_from_n(2) <= hibi_we_out_from_the_n2h2_chan_2;
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126
  hibi_av_in_to_the_n2h2_chan_0 <= av_to_n(0);
127
  hibi_av_in_to_the_n2h2_chan_1 <= av_to_n(1);
128
  hibi_av_in_to_the_n2h2_chan_2 <= av_to_n(2);
129
 
130
  hibi_comm_in_to_the_n2h2_chan_0 <= comm_to_n(5*1-1 downto 5*0);
131
  hibi_comm_in_to_the_n2h2_chan_1 <= comm_to_n(5*2-1 downto 5*1);
132
  hibi_comm_in_to_the_n2h2_chan_2 <= comm_to_n(5*3-1 downto 5*2);
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134
  hibi_data_in_to_the_n2h2_chan_0 <= data_to_n(32*1-1 downto 32*0);
135
  hibi_data_in_to_the_n2h2_chan_1 <= data_to_n(32*2-1 downto 32*1);
136
  hibi_data_in_to_the_n2h2_chan_2 <= data_to_n(32*3-1 downto 32*2);
137
 
138
  hibi_empty_in_to_the_n2h2_chan_0 <= empty_to_n(0);
139
  hibi_empty_in_to_the_n2h2_chan_1 <= empty_to_n(1);
140
  hibi_empty_in_to_the_n2h2_chan_2 <= empty_to_n(2);
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142
  hibi_full_in_to_the_n2h2_chan_0 <= full_to_n(0);
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  hibi_full_in_to_the_n2h2_chan_1 <= full_to_n(1);
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  hibi_full_in_to_the_n2h2_chan_2 <= full_to_n(2);
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148
  hibiv3_r4_1: entity work.hibiv3_r4
149
    generic map (
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      id_width_g          => 6,
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      addr_width_g        => 32,
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      data_width_g        => 32,
153
      comm_width_g        => 5,
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      counter_width_g     => 8,
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      rel_agent_freq_g    => 1,
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      rel_bus_freq_g      => 1,
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      arb_type_g          => 3,
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      fifo_sel_g          => 0,
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      rx_fifo_depth_g     => 4,
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      rx_msg_fifo_depth_g => 4,
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      tx_fifo_depth_g     => 4,
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      tx_msg_fifo_depth_g => 4,
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      max_send_g          => 20,
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      n_cfg_pages_g       => 1,
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      n_time_slots_g      => 0,
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      keep_slot_g         => 0,
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      n_extra_params_g    => 1,
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      cfg_re_g            => 1,
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      cfg_we_g            => 1,
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      debug_width_g       => 1,
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      n_agents_g          => 3,
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      n_segments_g        => 1,
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      separate_addr_g     => 0)
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    port map (
175
      clk_ip          => clk_0,
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      clk_noc         => clk_0,
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      rst_n           => reset_n,
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      agent_comm_in   => comm_from_n,
179
      agent_data_in   => data_from_n,
180
      agent_av_in     => av_from_n,
181
      agent_we_in     => we_from_n,
182
      agent_re_in     => re_from_n,
183
      agent_comm_out  => comm_to_n,
184
      agent_data_out  => data_to_n,
185
      agent_av_out    => av_to_n,
186
      agent_full_out  => full_to_n,
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      agent_one_p_out => one_p_to_n,
188
      agent_empty_out => empty_to_n,
189
      agent_one_d_out => one_d_to_n);
190
 
191
 
192
  cpu_reset_p: process
193
  begin  -- process cpu_reset_p
194
 
195
    cpu_0_reset <= '1';
196
    cpu_1_reset <= '1';
197
    cpu_2_reset <= '1';
198
 
199
    wait for 100 us;
200
 
201
    cpu_0_reset <= '0';
202
    cpu_1_reset <= '0';
203
    cpu_2_reset <= '0';
204
 
205
    wait;
206
 
207
  end process cpu_reset_p;
208
 
209
 
210
-- AND HERE WILL BE PRESERVED </ALTERA_NOTE>
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212
 
213
end europa;
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--synthesis translate_on

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