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-------------------------------------------------------------------------------
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-- Title : Functions for ase_mesh1 and wrappers using it
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-- Project :
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-------------------------------------------------------------------------------
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-- File : ase_mesh1_pkg.vhdl
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-- Author : Lasse Lehtonen
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-- Company :
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-- Created : 2010-06-16
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-- Last update: 2012-03-31
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-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2010
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2010-06-16 1.0 ase Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.log2_pkg.all;
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-------------------------------------------------------------------------------
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-- PACKAGE DECLARATION
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-------------------------------------------------------------------------------
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package ase_mesh1_pkg is
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-----------------------------------------------------------------------------
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-- HELPER FUCTIONS
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-----------------------------------------------------------------------------
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-- Returns target address (ase_mesh1 network address)
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pure function ase_mesh1_address (
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src_id : in integer; -- Source agent id number
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dst_id : in integer; -- Destination agent id number
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rows : in positive;
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cols : in positive;
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bus_width : in positive)
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return std_logic_vector;
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end package ase_mesh1_pkg;
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-------------------------------------------------------------------------------
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-- PACKAGE BODY
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-------------------------------------------------------------------------------
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package body ase_mesh1_pkg is
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pure function ase_mesh1_address (
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constant src_id : in integer; -- Source agent id number
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constant dst_id : in integer; -- Destination agent id number
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constant rows : in positive;
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constant cols : in positive;
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constant bus_width : in positive)
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return std_logic_vector is
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variable retval : std_logic_vector(bus_width-1 downto 0);
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variable lr_bit : std_logic;
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variable here_bit : std_logic;
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variable first_dir : std_logic_vector(1 downto 0);
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variable src_row : integer;
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variable src_col : integer;
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variable dst_row : integer;
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variable dst_col : integer;
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constant mesh1_row_width_c : positive := log2_ceil(rows - 1);
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constant mesh1_col_width_c : positive := log2_ceil(cols - 1);
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constant mesh1_port_width_c : positive :=
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bus_width - mesh1_row_width_c - mesh1_col_width_c - 4;
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variable dst_port : integer := 0;
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begin
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retval := (others => '0');
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lr_bit := '0';
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here_bit := '0';
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first_dir := "00";
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src_row := (src_id / cols);
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src_col := src_id - (src_row * cols);
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dst_row := (dst_id / cols);
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dst_col := dst_id - (dst_row * cols);
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-- if src_id = 7 then
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-- report "srow " & integer'image(src_row) & ", drow "
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-- & integer'image(dst_row) & ", scol "
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-- & integer'image(src_col) & ", dcol "
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-- & integer'image(dst_col) & ", cols "
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-- & integer'image(cols) & ", rows "
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-- & integer'image(rows)
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-- severity note;
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-- end if;
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retval(bus_width-1 downto bus_width-mesh1_port_width_c) :=
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std_logic_vector(to_unsigned(dst_port, mesh1_port_width_c));
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if src_row = dst_row then
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if src_col = dst_col then
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elsif src_col < dst_col then
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first_dir := "01";
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
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else
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first_dir := "11";
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
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end if;
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elsif src_row < dst_row then
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first_dir := "10";
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retval(mesh1_row_width_c-1 downto 0) :=
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std_logic_vector
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(to_unsigned
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((2**mesh1_row_width_c)-(dst_row-src_row), mesh1_row_width_c));
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if src_col = dst_col then
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here_bit := '1';
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elsif src_col < dst_col then
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
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else
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lr_bit := '1';
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
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end if;
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else
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first_dir := "00";
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retval(mesh1_row_width_c-1 downto 0) :=
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std_logic_vector
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(to_unsigned
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((2**mesh1_row_width_c)-(src_row-dst_row), mesh1_row_width_c));
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if src_col = dst_col then
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here_bit := '1';
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elsif src_col < dst_col then
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(dst_col-src_col), mesh1_col_width_c));
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else
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lr_bit := '1';
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retval(mesh1_row_width_c+mesh1_col_width_c-1 downto mesh1_row_width_c)
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:= std_logic_vector
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(to_unsigned
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((2**mesh1_col_width_c)-(src_col-dst_col), mesh1_col_width_c));
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end if;
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end if;
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retval(mesh1_row_width_c+mesh1_col_width_c+0) := lr_bit;
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retval(mesh1_row_width_c+mesh1_col_width_c+1) := here_bit;
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retval(mesh1_row_width_c+mesh1_col_width_c+2) := first_dir(0);
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retval(mesh1_row_width_c+mesh1_col_width_c+3) := first_dir(1);
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return retval;
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end function ase_mesh1_address;
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end package body ase_mesh1_pkg;
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