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-------------------------------------------------------------------------------
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-- Title : Mesh configuration package
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-- Project :
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-------------------------------------------------------------------------------
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-- File : ase_noc_pkg.vhd
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-- Author : Lasse Lehtonen
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-- Company :
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-- Created : 2011-01-18
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-- Last update: 2011-11-08
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-- Platform :
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-- Standard : VHDL'93
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2011-01-18 1.0 lehton87 Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.log2_pkg.all;
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package ase_noc_pkg is
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-- Commands
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constant mesh_cmd_idle_c : std_logic_vector(1 downto 0) := "00";
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constant mesh_cmd_addr_c : std_logic_vector(1 downto 0) := "01";
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constant mesh_cmd_data_c : std_logic_vector(1 downto 0) := "10";
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constant mesh_cmd_empty_c : std_logic_vector(1 downto 0) := "11";
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-- Helper functions
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function ase_noc_address (
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constant own_id : in natural;
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constant target_id : in natural;
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constant mesh_cols_c : in positive;
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constant mesh_rows_c : in positive;
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constant mesh_agent_ports_c : in positive;
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constant mesh_data_width_c : in positive)
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return std_logic_vector;
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function ase_noc_address_s (
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constant own_id : in natural;
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signal target_id : in integer;
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constant mesh_cols_c : in positive;
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constant mesh_rows_c : in positive;
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constant mesh_agent_ports_c : in positive;
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constant mesh_data_width_c : in positive)
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return std_logic_vector;
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end package ase_noc_pkg;
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package body ase_noc_pkg is
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function ase_noc_address (
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constant own_id : in natural;
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constant target_id : in natural;
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constant mesh_cols_c : in positive;
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constant mesh_rows_c : in positive;
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constant mesh_agent_ports_c : in positive;
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constant mesh_data_width_c : in positive)
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return std_logic_vector is
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variable ret : std_logic_vector(mesh_data_width_c-1 downto 0);
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variable src_row : natural range 0 to mesh_rows_c-1;
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variable src_col : natural range 0 to mesh_cols_c-1;
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variable dst_row : natural range 0 to mesh_rows_c-1;
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variable dst_col : natural range 0 to mesh_cols_c-1;
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variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1;
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variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1;
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variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1;
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constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c);
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constant mesh_ids_c : natural :=
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mesh_rows_c*mesh_cols_c*mesh_agent_ports_c;
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constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1);
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constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1);
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begin -- function mesh_address
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ret := (others => '0');
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src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c));
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src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c));
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dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c));
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dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c));
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col_dif := dst_col - src_col;
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row_dif := dst_row - src_row;
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dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4;
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if src_row = dst_row then
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if src_col = dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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elsif src_col < dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(1, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
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mesh_col_add_c));
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ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
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mesh_col_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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else
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(3, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
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mesh_col_add_c));
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ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
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mesh_col_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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end if;
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elsif src_row < dst_row then
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if src_col = dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(2, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
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mesh_row_add_c));
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ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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elsif src_col < dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(2, mesh_port_width_c));
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ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
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mesh_row_add_c));
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ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(1, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_port_width_c*2+mesh_row_add_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
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mesh_col_add_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
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mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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else
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(2, mesh_port_width_c));
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ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
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mesh_row_add_c));
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ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(3, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_port_width_c*2+mesh_row_add_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
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mesh_col_add_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
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mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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end if;
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else
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if src_col = dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(0, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
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mesh_row_add_c));
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ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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elsif src_col < dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(0, mesh_port_width_c));
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ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
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mesh_row_add_c));
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ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(1, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_port_width_c*2+mesh_row_add_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
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mesh_col_add_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
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mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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else
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(0, mesh_port_width_c));
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ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
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std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
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mesh_row_add_c));
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ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_row_add_c+mesh_port_width_c) :=
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std_logic_vector(to_unsigned(3, mesh_port_width_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
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mesh_port_width_c*2+mesh_row_add_c) :=
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std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
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mesh_col_add_c));
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ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
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mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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end if;
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end if;
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report "From " & integer'image(own_id) & " to " & integer'image(target_id)
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& " gives " & integer'image(to_integer(unsigned(ret))) severity note;
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report "col_add " & integer'image(mesh_col_add_c)
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& ", row_add " & integer'image(mesh_row_add_c)
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& ", port_w " & integer'image(mesh_port_width_c) severity note;
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return ret;
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end function ase_noc_address;
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function ase_noc_address_s (
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constant own_id : in natural;
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signal target_id : in integer;
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constant mesh_cols_c : in positive;
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constant mesh_rows_c : in positive;
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constant mesh_agent_ports_c : in positive;
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constant mesh_data_width_c : in positive)
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return std_logic_vector is
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variable ret : std_logic_vector(mesh_data_width_c-1 downto 0);
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variable src_row : natural range 0 to mesh_rows_c-1;
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variable src_col : natural range 0 to mesh_cols_c-1;
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variable dst_row : natural range 0 to mesh_rows_c-1;
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variable dst_col : natural range 0 to mesh_cols_c-1;
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variable col_dif : integer range -mesh_cols_c/2-1 to mesh_cols_c/2+1;
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variable row_dif : integer range -mesh_rows_c/2-1 to mesh_rows_c/2+1;
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variable dst_port : natural range 4 to 4+mesh_agent_ports_c-1;
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constant mesh_port_width_c : natural := log2_ceil(4+mesh_agent_ports_c);
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constant mesh_ids_c : natural :=
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mesh_rows_c*mesh_cols_c*mesh_agent_ports_c;
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constant mesh_col_add_c : natural := log2_ceil(mesh_cols_c-1);
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constant mesh_row_add_c : natural := log2_ceil(mesh_rows_c-1);
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begin -- function mesh_address
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ret := (others => '0');
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src_row := (own_id / (mesh_cols_c * mesh_agent_ports_c));
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src_col := own_id - (src_row * (mesh_cols_c * mesh_agent_ports_c));
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dst_row := (target_id / (mesh_cols_c * mesh_agent_ports_c));
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dst_col := target_id - (dst_row * (mesh_cols_c * mesh_agent_ports_c));
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col_dif := dst_col - src_col;
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row_dif := dst_row - src_row;
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dst_port := target_id - (dst_row*mesh_cols_c+dst_col)*mesh_agent_ports_c+4;
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if src_row = dst_row then
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if src_col = dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
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elsif src_col < dst_col then
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ret(mesh_port_width_c-1 downto 0) :=
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| 283 |
|
|
std_logic_vector(to_unsigned(1, mesh_port_width_c));
|
| 284 |
|
|
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 285 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
|
| 286 |
|
|
mesh_col_add_c));
|
| 287 |
|
|
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
|
| 288 |
|
|
mesh_col_add_c+mesh_port_width_c) :=
|
| 289 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 290 |
|
|
|
| 291 |
|
|
else
|
| 292 |
|
|
|
| 293 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 294 |
|
|
std_logic_vector(to_unsigned(3, mesh_port_width_c));
|
| 295 |
|
|
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 296 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
|
| 297 |
|
|
mesh_col_add_c));
|
| 298 |
|
|
ret(mesh_port_width_c+mesh_col_add_c+mesh_port_width_c-1 downto
|
| 299 |
|
|
mesh_col_add_c+mesh_port_width_c) :=
|
| 300 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 301 |
|
|
|
| 302 |
|
|
end if;
|
| 303 |
|
|
|
| 304 |
|
|
elsif src_row < dst_row then
|
| 305 |
|
|
|
| 306 |
|
|
if src_col = dst_col then
|
| 307 |
|
|
|
| 308 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 309 |
|
|
std_logic_vector(to_unsigned(2, mesh_port_width_c));
|
| 310 |
|
|
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 311 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
|
| 312 |
|
|
mesh_row_add_c));
|
| 313 |
|
|
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
|
| 314 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 315 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 316 |
|
|
|
| 317 |
|
|
elsif src_col < dst_col then
|
| 318 |
|
|
|
| 319 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 320 |
|
|
std_logic_vector(to_unsigned(2, mesh_port_width_c));
|
| 321 |
|
|
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 322 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
|
| 323 |
|
|
mesh_row_add_c));
|
| 324 |
|
|
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 325 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 326 |
|
|
std_logic_vector(to_unsigned(1, mesh_port_width_c));
|
| 327 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 328 |
|
|
mesh_port_width_c*2+mesh_row_add_c) :=
|
| 329 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
|
| 330 |
|
|
mesh_col_add_c));
|
| 331 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
|
| 332 |
|
|
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
|
| 333 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 334 |
|
|
|
| 335 |
|
|
else
|
| 336 |
|
|
|
| 337 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 338 |
|
|
std_logic_vector(to_unsigned(2, mesh_port_width_c));
|
| 339 |
|
|
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 340 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c-row_dif,
|
| 341 |
|
|
mesh_row_add_c));
|
| 342 |
|
|
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 343 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 344 |
|
|
std_logic_vector(to_unsigned(3, mesh_port_width_c));
|
| 345 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 346 |
|
|
mesh_port_width_c*2+mesh_row_add_c) :=
|
| 347 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
|
| 348 |
|
|
mesh_col_add_c));
|
| 349 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
|
| 350 |
|
|
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
|
| 351 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 352 |
|
|
|
| 353 |
|
|
end if;
|
| 354 |
|
|
|
| 355 |
|
|
else
|
| 356 |
|
|
|
| 357 |
|
|
if src_col = dst_col then
|
| 358 |
|
|
|
| 359 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 360 |
|
|
std_logic_vector(to_unsigned(0, mesh_port_width_c));
|
| 361 |
|
|
ret(mesh_col_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 362 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
|
| 363 |
|
|
mesh_row_add_c));
|
| 364 |
|
|
ret(mesh_port_width_c+mesh_row_add_c+mesh_port_width_c-1 downto
|
| 365 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 366 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 367 |
|
|
|
| 368 |
|
|
elsif src_col < dst_col then
|
| 369 |
|
|
|
| 370 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 371 |
|
|
std_logic_vector(to_unsigned(0, mesh_port_width_c));
|
| 372 |
|
|
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 373 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
|
| 374 |
|
|
mesh_row_add_c));
|
| 375 |
|
|
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 376 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 377 |
|
|
std_logic_vector(to_unsigned(1, mesh_port_width_c));
|
| 378 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 379 |
|
|
mesh_port_width_c*2+mesh_row_add_c) :=
|
| 380 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c-col_dif,
|
| 381 |
|
|
mesh_col_add_c));
|
| 382 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
|
| 383 |
|
|
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
|
| 384 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 385 |
|
|
|
| 386 |
|
|
else
|
| 387 |
|
|
|
| 388 |
|
|
ret(mesh_port_width_c-1 downto 0) :=
|
| 389 |
|
|
std_logic_vector(to_unsigned(0, mesh_port_width_c));
|
| 390 |
|
|
ret(mesh_row_add_c+mesh_port_width_c-1 downto mesh_port_width_c) :=
|
| 391 |
|
|
std_logic_vector(to_unsigned(2**mesh_row_add_c+row_dif,
|
| 392 |
|
|
mesh_row_add_c));
|
| 393 |
|
|
ret(mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 394 |
|
|
mesh_row_add_c+mesh_port_width_c) :=
|
| 395 |
|
|
std_logic_vector(to_unsigned(3, mesh_port_width_c));
|
| 396 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2-1 downto
|
| 397 |
|
|
mesh_port_width_c*2+mesh_row_add_c) :=
|
| 398 |
|
|
std_logic_vector(to_unsigned(2**mesh_col_add_c+col_dif,
|
| 399 |
|
|
mesh_col_add_c));
|
| 400 |
|
|
ret(mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*3-1 downto
|
| 401 |
|
|
mesh_col_add_c+mesh_row_add_c+mesh_port_width_c*2) :=
|
| 402 |
|
|
std_logic_vector(to_unsigned(dst_port, mesh_port_width_c));
|
| 403 |
|
|
|
| 404 |
|
|
end if;
|
| 405 |
|
|
|
| 406 |
|
|
end if;
|
| 407 |
|
|
|
| 408 |
|
|
return ret;
|
| 409 |
|
|
|
| 410 |
|
|
end function ase_noc_address_s;
|
| 411 |
|
|
|
| 412 |
|
|
|
| 413 |
|
|
|
| 414 |
|
|
end package body ase_noc_pkg;
|
