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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [altera_de2_pll_25/] [1.0/] [ip-xact/] [altera_de2_pll_25.1.0.xml] - Blame information for rev 145

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1 145 lanttu
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        TUT
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        ip.hwp.misc
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        altera_de2_pll_25
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        1.0
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        25 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 2)
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                        clk_in
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                        clk_in
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                        Input clock (50 MHz, DE2 PIN_N2)
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                inclk0
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                                                        0
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                                                        0
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                        8
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                        little
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                        clk_out
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                        clk_out
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                        Output clock: input clock divided by 2.
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                c0
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                                                        0
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                                                        0
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                        8
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                        little
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                                rtl
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                                vhdl::
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                                        HDLsources
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                                c0
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                                inclk0
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        rtl
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                        HDLsources
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                        HDL sources
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                        HDL sources.
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                                ../vhd/ALTPLL_for_DE2_50to25.vhd
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                                vhdlSource
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                                false
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                                work
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                                        false
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                                vhdlSource
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                                vcom
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                                -work work -check_synthesis -quiet
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                                false
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                                Global
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                                Mutable
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