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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [clock/] [1.0/] [ip_xact/] [clk_gen.1.0.xml] - Blame information for rev 145

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        TUT
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        ip.hwp.interface
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        clk_gen
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        1.0
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        Simple clock generator dor simulation.
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                        Generated_clk
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk_out
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                                                        0
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                                                        0
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                        8
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                        little
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                        Generated_hibi_clk
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                        false
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                                                AGENT_SYNC_CLK
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                                                        0
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                                                        0
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                                                clk_out
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                                                        0
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                                                        0
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                                                BUS_CLK
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                                                        0
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                                                        0
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                                                clk_out
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                                                        0
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                                                        0
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                                                BUS_SYNC_CLK
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                                                        0
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                                                        0
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                                                clk_out
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                                                        0
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                                                        0
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                                                AGENT_CLK
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                                                        0
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                                                        0
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                                                clk_out
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                                                        0
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                                                        0
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                        8
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                        little
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                                behavioral
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                                VHDL::Not
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                                        behavioral
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                                clk_out
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                                        out
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                                hi_period_ns_g
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                                1
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                                lo_period_ns_g
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                                1
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                        behavioral
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                                ../vhd/clk_gen.vhd
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                                vhdlSource
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                                false
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                                work
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                                vhdlSource
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                                vcom
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                                -check_synthesis
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                                false
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                                IP
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                                HW
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                                Template
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