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-------------------------------------------------------------------------------
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-- Title : Communication module for the LAN91C111 controller
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-- Project :
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-------------------------------------------------------------------------------
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-- File : Lan91c111_comm_module.vhd
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-- Author : Jussi Nieminen, Antti Alhonen
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-- Last update: 2011-11-06
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009/08/21 1.0 niemin95 Created
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-- 2011/07/17 2.0 alhonena Modified for LAN91C111
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.lan91c111_ctrl_pkg.all;
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entity lan91c111_comm_module is
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port (
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clk : in std_logic; -- 25 MHz
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rst_n : in std_logic;
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comm_requests_in : in std_logic_vector( submodules_c-1 downto 0 );
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comm_grants_out : out std_logic_vector( submodules_c-1 downto 0 );
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interrupt_out : out std_logic;
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init_ready_in : in std_logic;
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-- interface to submodules (and to init block)
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register_addrs_in : in std_logic_vector( (submodules_c+1) * real_addr_width_c - 1 downto 0 ); -- from each submodule
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config_datas_in : in std_logic_vector( (submodules_c+1) * lan91_data_width_c - 1 downto 0 );
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config_nBEs_in : in std_logic_vector( (submodules_c+1) * 4 - 1 downto 0 );
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read_not_write_in : in std_logic_vector( submodules_c downto 0 );
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configs_valid_in : in std_logic_vector( submodules_c downto 0 );
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data_to_submodules_out : out std_logic_vector( lan91_data_width_c - 1 downto 0 );
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data_to_sb_valid_out : out std_logic;
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busy_to_submodules_out : out std_logic;
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-- interface to LAN91C111
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eth_data_inout : inout std_logic_vector( lan91_data_width_c-1 downto 0 );
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eth_addr_out : out std_logic_vector( lan91_addr_width_c-1 downto 0 );
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eth_interrupt_in : in std_logic;
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eth_read_out : out std_logic;
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eth_write_out : out std_logic;
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eth_nADS_out : out std_logic;
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eth_nAEN_out : out std_logic;
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eth_nBE_out : out std_logic_vector(3 downto 0)
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);
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end lan91c111_comm_module;
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architecture rtl of lan91c111_comm_module is
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-- Major change compared to DM9000A controller by Jussi Nieminen;
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-- Data muxes between "config_data", "tx data" and "rx data" have
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-- been moved completely to the Send and Read modules; this module takes only
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-- one type of input from Send and Read, not two types. Hence, this
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-- module is simplified a lot.
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-- The major reason for the change is that whereas DM9000A does not include
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-- "register address" for every write/read operation, LAN91C111 does; all
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-- data is accessed via a single register address, pointed by a separate
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-- pointer register with its own address.
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-- WRITING AND READING PROCEDURES by comm_state_r
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-- wait_valid:
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-- Wait until one of the submodules wants to write or read. Immediately put
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-- the address (and data in case of write) on the busses and go to write_data
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-- or read_data, which asserts write or read enable signal to the chip.
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--
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-- write_data:
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-- Set write_out low. Go to data_written.
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--
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-- read_data:
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-- Set read_out low. Go to data_read.
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--
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-- data_written:
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-- Set write_out high. Go to wait_valid.
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--
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-- data_read:
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-- Read the data. Set read_out high. Go to wait_valid.
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--
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-- Example of the read operation:
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-- |1 |2 |3 |4 |5 |6 |
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-- config_valid_in ___----------------
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-- readnotwrite ___----------------
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-- addr_out xxxxxx< ADDR >xxxx (valid for 3 cycles)
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-- data_out xxxxxxZZZZZZZZZxxxx (valid for 3 cycles)
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-- nEth_read_out ---------___------ (1 cycle long in the middle)
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-- Read data here: <> (on the rising edge of read enable signal)
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--
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-- Example of the write operation:
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-- |1 |2 |3 |4 |5 |6 |
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-- config_valid_in ___----------------
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-- readnotwrite ___________________
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-- addr_out xxxxxx< ADDR >xxxx (valid for 3 cycles)
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-- data_out xxxxxx< DATA >xxxx (valid for 3 cycles)
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-- nEth_write_out ---------___------ (1 cycle long in the middle)
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type comm_state_type is (wait_valid, write_data, data_written, read_data, data_read);
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signal comm_state_r : comm_state_type;
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-- Arbiter side selects one of the incoming communication requests and feeds
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-- data to these:
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signal register_addr : std_logic_vector( real_addr_width_c-1 downto 0 );
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signal config_data : std_logic_vector( lan91_data_width_c-1 downto 0 );
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signal config_nBE : std_logic_vector( 3 downto 0 );
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signal read_not_write : std_logic; -- 1 = read, 0 = write
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signal config_valid : std_logic;
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signal comm_grants_r : std_logic_vector( submodules_c-1 downto 0 );
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-------------------------------------------------------------------------------
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begin -- rtl
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-------------------------------------------------------------------------------
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-- concurrent assignments
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comm_grants_out <= comm_grants_r;
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interrupt_out <= eth_interrupt_in;
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eth_nADS_out <= '0';
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eth_nAEN_out <= '0';
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arbitration: process (clk, rst_n)
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variable reserved_v : std_logic;
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begin -- process arbitration
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if rst_n = '0' then -- asynchronous reset (active low)
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comm_grants_r <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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reserved_v := '0';
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if init_ready_in = '1' then
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-- can't use 'others' in comparison, so we do it this way
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if comm_grants_r = std_logic_vector( to_unsigned( 0, submodules_c )) then
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-- no one is using comm_module right now
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-- lowest index wins
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for n in 0 to submodules_c-1 loop
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if comm_requests_in(n) = '1' then
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if reserved_v = '0' then
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comm_grants_r(n) <= '1';
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reserved_v := '1';
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end if;
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end if;
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end loop; -- n
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else
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-- clear grant when request goes out
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for n in 0 to submodules_c-1 loop
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if comm_grants_r(n) = '1' and comm_requests_in(n) = '0' then
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comm_grants_r(n) <= '0';
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end if;
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end loop; -- n
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end if;
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else
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-- no grants during initialization
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comm_grants_r <= (others => '0');
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end if;
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end if;
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end process arbitration;
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submodule_mux: process (comm_grants_r, register_addrs_in, config_datas_in, config_nBEs_in,
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read_not_write_in, configs_valid_in, init_ready_in)
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begin -- process submodule_mux
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if init_ready_in = '0' then
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-- init block has the highest index, but it doesn't compete for it's turn
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register_addr <= register_addrs_in( (submodules_c+1)*real_addr_width_c - 1 downto submodules_c*real_addr_width_c );
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config_data <= config_datas_in( (submodules_c+1)*lan91_data_width_c - 1 downto submodules_c*lan91_data_width_c );
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config_nBE <= config_nBEs_in( (submodules_c+1)*4 - 1 downto submodules_c*4 );
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read_not_write <= read_not_write_in( submodules_c );
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config_valid <= configs_valid_in( submodules_c );
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else
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-- init ready, normal arbitration
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-- default:
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register_addr <= (others => '0');
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config_data <= (others => '0');
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config_nBE <= (others => '0');
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read_not_write <= '0';
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config_valid <= '0';
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-- grant signal decides
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for n in 0 to submodules_c-1 loop
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if comm_grants_r(n) = '1' then
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register_addr <= register_addrs_in( (n+1)*real_addr_width_c - 1 downto n*real_addr_width_c );
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config_data <= config_datas_in( (n+1)*lan91_data_width_c - 1 downto n*lan91_data_width_c );
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config_nBE <= config_nBEs_in( (n+1)*4 - 1 downto n*4 );
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read_not_write <= read_not_write_in(n);
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config_valid <= configs_valid_in(n);
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end if;
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end loop; -- n
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end if;
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end process submodule_mux;
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lan91c111_communication: process (clk, rst_n)
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begin -- process lan91c111_communication
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if rst_n = '0' then -- asynchronous reset (active low)
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eth_write_out <= '1';
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eth_read_out <= '1';
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eth_data_inout <= (others => 'Z');
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data_to_submodules_out <= (others => '0');
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data_to_sb_valid_out <= '0';
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busy_to_submodules_out <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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-- defaults:
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eth_write_out <= '1'; -- remember, active low
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eth_read_out <= '1';
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data_to_sb_valid_out <= '0'; -- this is active high
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case comm_state_r is
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when wait_valid =>
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busy_to_submodules_out <= '0';
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if config_valid = '1' then
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busy_to_submodules_out <= '1';
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eth_addr_out <= base_addr_c & register_addr;
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if read_not_write = '1' then
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eth_data_inout <= (others => 'Z');
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comm_state_r <= read_data;
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else
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eth_data_inout <= config_data;
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comm_state_r <= write_data;
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end if;
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eth_nBE_out <= config_nBE;
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end if;
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when write_data =>
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eth_write_out <= '0';
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comm_state_r <= data_written;
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when data_written =>
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busy_to_submodules_out <= '0';
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comm_state_r <= wait_valid;
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when read_data =>
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eth_read_out <= '0';
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comm_state_r <= data_read;
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when data_read =>
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busy_to_submodules_out <= '0';
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-- read the data here:
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data_to_submodules_out <= eth_data_inout;
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data_to_sb_valid_out <= '1'; -- It is important that the
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-- busy_to_submodules_out goes low no
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-- later than valid goes high.
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-- Currently, the other modules rely on
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-- that to simplify the state machines.
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-- Also note that data_to_sb_valid_out is high only for one clock cycle
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-- and you must read the data immediately.
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-- eth_data_inout is left in high-impedance state. If needed for some
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-- reason, you can write something else to it here.
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comm_state_r <= wait_valid;
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when others => null;
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end case;
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end if;
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end process lan91c111_communication;
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end rtl;
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