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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [pll/] [1.0/] [pll.1.0.xml] - Blame information for rev 145

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        TUT
        ip.hwp.misc
        pll
        1.0
        50 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 1)
        
                
                        hibi_clk
                        hibi_clk
                        Output clock: input clock forwarded to the output.
                        
                        
                        
                        false
                        
                                
                                        
                                                AGENT_CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                AGENT_SYNC_CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                BUS_CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                                
                                        
                                                BUS_SYNC_CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        sdram_clk
                        sdram_clk
                        -54 degrees phase adjustment
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c1
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        clk_25MHz
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c2
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        clk_in
                        clk_in
                        Input clock (50 MHz, DE2 PIN_N2)
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                inclk0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        ip_clk
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                c0
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                rtl
                                vhdl::
                                
                                        HDLsources
                                
                        
                
                
                        
                                c0
                                
                                        out
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                                
                        
                        
                                c1
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                                
                        
                        
                                c2
                                
                                        out
                                
                                
                        
                        
                                inclk0
                                
                                        in
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        rtl
                                                
                                        
                                
                                
                        
                
        
        
                
                        HDLsources
                        HDL sources
                        HDL sources.
                        
                                hdl/pll.qip
                                quartusIPFile
                                false
                        
                        
                                hdl/pll.vhd
                                vhdlSource
                                false
                        
                
        
        
                
                        
                                Global
                                Mutable
                        
                
        


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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [pll/] [1.0/] [pll.1.0.xml] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4
5
6
7			`TUT`
8			`ip.hwp.misc`
9			`pll`
10			`1.0`
11			`50 MHz Altera ALTPLL instantiation for Cyclone II FPGA's with input clk of 50 MHz (mul = 1, div = 1)`
12
13
14			`hibi_clk`
15			`hibi_clk`
16			`Output clock: input clock forwarded to the output.`
17
18
19
20			`false`
21
22
23
24			`AGENT_CLK`
25
26			`0`
27			`0`
28
29
30
31			`c0`
32
33			`0`
34			`0`
35
36
37
38
39
40			`AGENT_SYNC_CLK`
41
42			`0`
43			`0`
44
45
46
47			`c0`
48
49			`0`
50			`0`
51
52
53
54
55
56			`BUS_CLK`
57
58			`0`
59			`0`
60
61
62
63			`c0`
64
65			`0`
66			`0`
67
68
69
70
71
72			`BUS_SYNC_CLK`
73
74			`0`
75			`0`
76
77
78
79			`c0`
80
81			`0`
82			`0`
83
84
85
86
87			`8`
88			`little`
89
90
91			`sdram_clk`
92			`sdram_clk`
93			`-54 degrees phase adjustment`
94
95
96
97			`false`
98
99
100
101			`CLK`
102
103			`0`
104			`0`
105
106
107
108			`c1`
109
110			`0`
111			`0`
112
113
114
115
116			`8`
117			`little`
118
119
120			`clk_25MHz`
121
122
123
124			`false`
125
126
127
128			`CLK`
129
130			`0`
131			`0`
132
133
134
135			`c2`
136
137			`0`
138			`0`
139
140
141
142
143			`8`
144			`little`
145
146
147			`clk_in`
148			`clk_in`
149			`Input clock (50 MHz, DE2 PIN_N2)`
150
151
152
153			`false`
154
155
156
157			`CLK`
158
159			`0`
160			`0`
161
162
163
164			`inclk0`
165
166			`0`
167			`0`
168
169
170
171
172			`8`
173			`little`
174
175
176			`ip_clk`
177
178
179
180			`false`
181
182
183
184			`CLK`
185
186			`0`
187			`0`
188
189
190
191			`c0`
192
193			`0`
194			`0`
195
196
197
198
199			`8`
200			`little`
201
202
203
204
205
206			`rtl`
207			`vhdl::`
208
209			`HDLsources`
210
211
212
213
214
215			`c0`
216
217			`out`
218
219
220			`std_logic`
221			`IEEE.std_logic_1164.all`
222			`rtl`
223
224
225
226
227
228
229			`c1`
230
231			`out`
232
233			`0`
234			`0`
235
236
237
238			`std_logic`
239			`IEEE.std_logic_1164.all`
240			`rtl`
241
242
243
244
245
246
247			`c2`
248
249			`out`
250
251
252
253
254			`inclk0`
255
256			`in`
257
258
259			`std_logic`
260			`IEEE.std_logic_1164.all`
261			`rtl`
262
263
264
265
266
267
268
269
270
271			`HDLsources`
272			`HDL sources`
273			`HDL sources.`
274
275			`hdl/pll.qip`
276			`quartusIPFile`
277			`false`
278
279
280			`hdl/pll.vhd`
281			`vhdlSource`
282			`false`
283
284
285
286
287
288
289			`Global`
290			`Mutable`
291
292
293
294