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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [switch_pkt_codec_mk2/] [1.0/] [ip_xact/] [switch_pkt_codec_mk2.1.0.xml] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu
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        TUT
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        ip.hwp.interface
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        switch_pkt_codec_mk2
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        1.0
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                        clock
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk
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                                                        0
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                                                        0
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                        8
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                        little
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                        pkt_codec_mk2
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                        false
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                                                STALL_IN
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                                                        0
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                                                        0
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                                                stall_out
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                                                        0
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                                                        0
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                                                DATA_OUT
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                                                        31
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                                                        0
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                                                data_in
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                                                        0
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                                                CMD_OUT
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                                                        0
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                                                cmd_in
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                                                stall_in
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                                                DATA_IN
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                                                data_out
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                                                CMD_IN
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                                                cmd_out
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                                                        0
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                        8
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                        little
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                        reset
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                        false
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                                                RESETn
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                                                        0
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                                                        0
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                                                rst_n
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                                                        0
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                                                        0
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                        8
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                        little
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                        switch
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                        false
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                                                gpio
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                                                        0
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                                                        0
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                                                switch_in
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                                                        0
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                                                        0
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                        8
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                        little
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                                hdl
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                                VHDL::
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                                        HDLsource
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                                clk
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                                        in
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                                                0
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                                                0
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                cmd_in
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                                        in
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                                                1
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                cmd_out
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                                        out
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                                                1
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data_in
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                                        in
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                data_out
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                                        out
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                                                31
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                                                0
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                                                        std_logic_vector
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                rst_n
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall_in
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                stall_out
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                                        out
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                switch_in
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                                        in
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                                                        std_logic
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                                                        IEEE.std_logic_1164.all
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                                                        hdl
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                                target_id_g
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                                target_id in the noc
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                                0
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                        HDLsource
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                                ../vhd/switch_pkt_codec_mk2.vhd
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                                vhdlSource
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                                false
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                                work
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                                        false
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                                vhdlSource
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                                vcom
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                                -quiet -check_synthesis
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                                false
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        Sends a constant addr+data pair every time a switch is toggled.
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                                IP
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                                HW
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                                Fixed
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