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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [udp2hibi/] [1.0/] [tb/] [tb_udp2hibi.vhd] - Blame information for rev 183

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1 145 lanttu
-------------------------------------------------------------------------------
2
-- Title      : Testbench for udp2hibi toplevel
3
-- Project    : UDP2HIBI
4
-------------------------------------------------------------------------------
5
-- File       : tb_udp2hibi.vhd
6
-- Author     : Jussi Nieminen
7
-- Last update: 2012-03-23
8
-- Platform   : Sim only
9
-------------------------------------------------------------------------------
10
-- Description: Simple hard-coded directed test stimulus  generation without
11
--              automated checking.
12
-------------------------------------------------------------------------------
13
-- Revisions  :
14
-- Date        Version  Author  Description
15
-- 2009/12/15  1.0      niemin95        Created
16
-------------------------------------------------------------------------------
17
 
18
library ieee;
19
use ieee.std_logic_1164.all;
20
use ieee.numeric_std.all;
21
use work.udp2hibi_pkg.all;
22
 
23
entity tb_udp2hibi is
24
end tb_udp2hibi;
25
 
26
 
27
architecture tb of tb_udp2hibi is
28
 
29
  --
30
  -- Structure: DUV + 3 processes
31
  --
32
  --                     +------>   udp_ip_reader
33
  --  hibi_traffic ---> DUV <---   udp_traffic 
34
  --                     | 
35
  -- (null="hibi") <-----/   
36
  --
37
 
38
 
39
  constant frequency_c     : integer   := 50_000_000;
40
  constant period_c        : time      := 20 ns;
41
  constant udp_ip_period_c : time      := 40 ns;  -- 40ns = 25 MHz
42
  signal   clk             : std_logic := '1';
43
  signal   clk_udp         : std_logic := '1';
44
  signal   rst_n           : std_logic := '0';
45
 
46
  constant hibi_comm_width_c : integer := 5;  --3;
47
  constant hibi_data_width_c : integer := 32;
48
  constant hibi_addr_width_c : integer := 32;
49
 
50
  constant receiver_table_size_c    : integer := 4;
51
  constant tx_multiclk_fifo_depth_c : integer := 10;
52
  constant rx_multiclk_fifo_depth_c : integer := 10;
53
  constant hibi_tx_fifo_depth_c     : integer := 10;
54
  constant ack_fifo_depth_c         : integer := 4;
55
 
56
 
57
  -- ** to/from HIBI **
58
  -- hibi receiver -> duv
59
  signal hibi_comm_to_duv  : std_logic_vector(hibi_comm_width_c-1 downto 0) := (others => '0');
60
  signal hibi_data_to_duv  : std_logic_vector(hibi_data_width_c-1 downto 0) := (others => '0');
61
  signal hibi_av_to_duv    : std_logic                                      := '0';
62
  signal hibi_empty_to_duv : std_logic                                      := '1';
63
  signal hibi_re_from_duv  : std_logic;
64
  signal hibi_re           : std_logic;  -- tb's internal signal
65
 
66
  -- duv -> "hibi" (nobody reads or checks these)
67
  signal hibi_comm_from_duv : std_logic_vector(hibi_comm_width_c-1 downto 0);
68
  signal hibi_data_from_duv : std_logic_vector(hibi_data_width_c-1 downto 0);
69
  signal hibi_av_from_duv   : std_logic;
70
  signal hibi_we_from_duv   : std_logic;
71
  signal hibi_full_to_duv   : std_logic := '0';
72
 
73
  -- ** to/from UDP/IP **
74
  -- tx
75
  signal tx_data_from_duv       : std_logic_vector(udp_block_data_w_c-1 downto 0);
76
  signal tx_data_valid_from_duv : std_logic;
77
  signal tx_re_to_duv           : std_logic                                       := '0';
78
  signal new_tx_from_duv        : std_logic;
79
  signal tx_len_from_duv        : std_logic_vector(tx_len_w_c-1 downto 0);
80
  signal dest_ip_from_duv       : std_logic_vector(ip_addr_w_c-1 downto 0);
81
  signal dest_port_from_duv     : std_logic_vector(udp_port_w_c-1 downto 0);
82
  signal source_port_from_duv   : std_logic_vector(udp_port_w_c-1 downto 0);
83
  -- rx
84
  signal rx_data_to_duv         : std_logic_vector(udp_block_data_w_c-1 downto 0) := (others => '0');
85
  signal rx_data_valid_to_duv   : std_logic                                       := '0';
86
  signal rx_re_from_duv         : std_logic;
87
  signal new_rx_to_duv          : std_logic                                       := '0';
88
  signal rx_len_to_duv          : std_logic_vector(tx_len_w_c-1 downto 0)         := (others => '0');
89
  signal source_ip_to_duv       : std_logic_vector(ip_addr_w_c-1 downto 0)        := (others => '0');
90
  signal dest_port_to_duv       : std_logic_vector(udp_port_w_c-1 downto 0)       := (others => '0');
91
  signal source_port_to_duv     : std_logic_vector(udp_port_w_c-1 downto 0)       := (others => '0');
92
  signal rx_erroneous_to_duv    : std_logic                                       := '0';
93
  -- udr rx completed, tb's internal signal
94
  signal udp_traffic_ready      : std_logic                                       := '0';
95
 
96
  -- *** test transfers ***
97
  -----------------------------------------------------------------------------
98
  -- Data types for outgoing test traffic
99
 
100
  type tx_data_type is array (integer range <>) of std_logic_vector(hibi_data_width_c-1 downto 0);
101
  type tx_info_type is
102
  record
103
    addr           : std_logic_vector(hibi_addr_width_c-1 downto 0);
104
    len            : integer;           -- 32b words
105
    data_16bit_len : integer;  -- 16b words, only in data tx, not in conf
106
    delay          : time;              -- after this tx
107
    data           : tx_data_type(0 to 28);  -- data values
108
  end record;
109
  signal current_tx : integer := 0;
110
 
111
  -----------------------------------------------------------------------------
112
  -- change these values, and array range of tx_info_type's data item to create
113
  -- new test traffic
114
 
115
  constant num_of_txs_c : integer := 7;
116
  type     test_txs_type is array (0 to num_of_txs_c-1) of tx_info_type;
117
 
118
  type     test_data_type is array (0 to 5) of std_logic_vector(15 downto 0);
119
  constant data1_c : test_data_type :=
120
    (x"0100", x"0302", x"0504", x"0706", x"0908", x"0a0b");
121
 
122
  constant test_txs_c : test_txs_type := (
123
    -- 0: tx_conf, this should get regs locked, results in ack=0x58... via hibi
124
    (addr => x"0123_4567", len => 4, data_16bit_len => 0, delay => 1 us,
125
     -- meaning of config data:    timeout,  dst ip addr,dst/src udp port,hibi addr for ack/nack/rxdata 
126
     data => (x"000_01234", x"acdc_abba", x"0101_aaaa", x"0082_faac", others => (others => '0'))),
127
 
128
    -- 1: an rx_conf results in ack=0x50... via hibi
129
    (addr => x"fedc_ba98", len => 4, data_16bit_len => 0, delay => 1 us,
130
     data => (x"3000_0000", x"1234_5678", x"3232_2323", x"0080_abba", others => (others => '0'))),
131
 
132
    -- 2: another rx_conf results in ack=0x50... via hibi
133
    (addr => x"fedc_ba98", len => 4, data_16bit_len => 0, delay => 1 us,
134
     data => (x"3000_0000", x"2345_6789", x"4343_3434", x"0080_beba", others => (others => '0'))),
135
 
136
    -- 3: start a tx by correct addr (107 bytes), these get written to udpip
137
    (addr => x"0123_4567", len => 28, data_16bit_len => 54, delay => 1 us,
138
 
139
     data                                                                                    => (x"1" & "00001101011" & "00000000000000000",
140
                                                                                      data1_c(1) & data1_c(0),  -- 1
141
                                                                                      data1_c(3) & data1_c(2),
142
                                                                                      data1_c(5) & data1_c(4),
143
                                                                                      data1_c(1) & data1_c(0),
144
                                                                                      data1_c(3) & data1_c(2),
145
                                                                                      data1_c(5) & data1_c(4),
146
                                                                                      data1_c(1) & data1_c(0),
147
                                                                                      data1_c(3) & data1_c(2),
148
                                                                                      data1_c(5) & data1_c(4),
149
                                                                                      data1_c(1) & data1_c(0),  -- 10
150
                                                                                      data1_c(3) & data1_c(2),
151
                                                                                      data1_c(5) & data1_c(4),
152
                                                                                      data1_c(1) & data1_c(0),
153
                                                                                      data1_c(3) & data1_c(2),
154
                                                                                      data1_c(5) & data1_c(4),
155
                                                                                      data1_c(1) & data1_c(0),
156
                                                                                      data1_c(3) & data1_c(2),
157
                                                                                      data1_c(5) & data1_c(4),
158
                                                                                      data1_c(1) & data1_c(0),
159
                                                                                      data1_c(3) & data1_c(2),  -- 20
160
                                                                                      data1_c(5) & data1_c(4),
161
                                                                                      data1_c(1) & data1_c(0),
162
                                                                                      data1_c(3) & data1_c(2),
163
                                                                                      data1_c(5) & data1_c(4),
164
                                                                                      data1_c(1) & data1_c(0),
165
                                                                                      data1_c(3) & data1_c(2),
166
                                                                                      data1_c(5) & data1_c(4),  -- 27
167
                                                                                      others => (others => '0'))),
168
 
169
    -- 4: start another small tx by correct addr (12 bytes), these get written to udpip
170
    (addr                                                                                                             => x"0123_4567", len => 4, data_16bit_len => 6, delay => 1 us,
171
     data                                                                                                             => (x"1" & "00000001100" & "00000000000000000",
172
                                                                                      data1_c(1) & data1_c(0),
173
                                                                                      data1_c(3) & data1_c(2),
174
                                                                                      data1_c(5) & data1_c(4), others => (others => '0'))),
175
 
176
 
177
    -- 5: illegal transfer, ulocked hibi addr, tx-ctrl assert prints a warning
178
    (addr                                                                                                             => x"1234_5678", len => 4, data_16bit_len => 6, delay => 1 us,
179
     data                                                                                                             => (x"1" & "00000001100" & "00000000000000000",
180
                                                                                      data1_c(1) & data1_c(0),
181
                                                                                      data1_c(3) & data1_c(2),
182
                                                                                      data1_c(5) & data1_c(4), others => (others => '0'))),
183
 
184
 
185
    -- 6: release the tx
186
    (addr => x"0123_4567", len => 1, data_16bit_len => 0, delay => 1 us,
187
     data => (x"2000_0000", others => (others => '0')))
188
    );
189
 
190
 
191
  -----------------------------------------------------------------------------
192
  -- ** incoming transfers **
193
 
194
  constant test_rx_data_amount_c : integer           := 16;
195
  type     test_rx_data_type is array (0 to test_rx_data_amount_c-1) of std_logic_vector(udp_block_data_w_c-1 downto 0);
196
  constant test_rx_data          : test_rx_data_type :=
197
    (x"0100", x"0302", x"0504", x"0706", x"0908", x"0b0a", x"0d0c", x"0f0e",
198
     x"1110", x"1312", x"1514", x"1716", x"1918", x"1b1a", x"1d1c", x"1f1e");
199
 
200
  type test_rxs_type is
201
  record
202
    source_ip         : std_logic_vector(ip_addr_w_c-1 downto 0);
203
    source_port       : std_logic_vector(udp_port_w_c-1 downto 0);
204
    dest_port         : std_logic_vector(udp_port_w_c-1 downto 0);
205
    rx_len            : integer;        -- 32b words
206
    rx_erroneous      : std_logic;
207
    delay_before_next : time;
208
  end record;
209
 
210
  constant num_of_rx_tests_c : integer := 5;
211
  type     test_rxs_array is array (0 to num_of_rx_tests_c-1) of test_rxs_type;
212
 
213
  -- test cases:
214
  -- 0. Normal (not erroneus, rx address valid) 200 bytes long packet
215
  -- 1. Packet without an receiver, src_ip does not match (should be dumped)
216
  -- 2. Erroneous packet (should also be dumped althogh ip&ports match)
217
  -- 3. Very short (1 byte) transfer with minimal delay
218
  -- 4. Normal incoming transfer following the earlier short one
219
  constant test_rxs : test_rxs_array :=
220
    ((source_ip         => x"1234_5678",
221
      source_port       => x"2323",
222
      dest_port         => x"3232",
223
      rx_len            => 50,
224
      rx_erroneous      => '0',
225
      delay_before_next => 100 * udp_ip_period_c),
226
     (source_ip         => x"00ff_0000",
227
      source_port       => x"2323",
228
      dest_port         => x"3232",
229
      rx_len            => 20,
230
      rx_erroneous      => '0',
231
      delay_before_next => 20 * udp_ip_period_c),
232
     (source_ip         => x"2345_6789",
233
      source_port       => x"3434",
234
      dest_port         => x"4343",
235
      rx_len            => 30,
236
      rx_erroneous      => '1',
237
      delay_before_next => 20 * udp_ip_period_c),
238
     (source_ip         => x"2345_6789",
239
      source_port       => x"3434",
240
      dest_port         => x"4343",
241
      rx_len            => 1,
242
      rx_erroneous      => '0',
243
      delay_before_next => udp_ip_period_c),
244
     (source_ip         => x"1234_5678",
245
      source_port       => x"2323",
246
      dest_port         => x"3232",
247
      rx_len            => 20,
248
      rx_erroneous      => '0',
249
      delay_before_next => 20 * udp_ip_period_c)
250
     );
251
 
252
 
253
  -- Two helper signal jutt for showing in wave window
254
  signal test_tx_id : integer;          -- ES 2012-03-23,
255
  signal test_rx_id : integer;          -- ES 2012-03-23
256
 
257
 
258
 
259
 
260
-------------------------------------------------------------------------------
261
begin  -- tb
262
-------------------------------------------------------------------------------
263
 
264
 
265
 
266
  duv : entity work.udp2hibi
267
    generic map (
268
      receiver_table_size_g    => receiver_table_size_c,
269
      ack_fifo_depth_g         => ack_fifo_depth_c,
270
      tx_multiclk_fifo_depth_g => tx_multiclk_fifo_depth_c,
271
      rx_multiclk_fifo_depth_g => rx_multiclk_fifo_depth_c,
272
      hibi_tx_fifo_depth_g     => hibi_tx_fifo_depth_c,
273
      hibi_data_width_g        => hibi_data_width_c,
274
      hibi_addr_width_g        => hibi_addr_width_c,
275
      hibi_comm_width_g        => hibi_comm_width_c,
276
      frequency_g              => frequency_c
277
      )
278
    port map (
279
      clk           => clk,
280
      clk_udp       => clk_udp,
281
      rst_n         => rst_n,
282
      hibi_comm_in  => hibi_comm_to_duv,
283
      hibi_data_in  => hibi_data_to_duv,
284
      hibi_av_in    => hibi_av_to_duv,
285
      hibi_empty_in => hibi_empty_to_duv,
286
      hibi_re_out   => hibi_re_from_duv,
287
 
288
      hibi_comm_out => hibi_comm_from_duv,
289
      hibi_data_out => hibi_data_from_duv,
290
      hibi_av_out   => hibi_av_from_duv,
291
      hibi_we_out   => hibi_we_from_duv,
292
      hibi_full_in  => hibi_full_to_duv,
293
 
294
      tx_data_out       => tx_data_from_duv,
295
      tx_data_valid_out => tx_data_valid_from_duv,
296
      tx_re_in          => tx_re_to_duv,
297
      new_tx_out        => new_tx_from_duv,
298
      tx_len_out        => tx_len_from_duv,
299
      dest_ip_out       => dest_ip_from_duv,
300
      dest_port_out     => dest_port_from_duv,
301
      source_port_out   => source_port_from_duv,
302
 
303
      rx_data_in       => rx_data_to_duv,
304
      rx_data_valid_in => rx_data_valid_to_duv,
305
      rx_re_out        => rx_re_from_duv,
306
      new_rx_in        => new_rx_to_duv,
307
      rx_len_in        => rx_len_to_duv,
308
      source_ip_in     => source_ip_to_duv,
309
      dest_port_in     => dest_port_to_duv,
310
      source_port_in   => source_port_to_duv,
311
      rx_erroneous_in  => rx_erroneous_to_duv,
312
      eth_link_up_in   => '1'
313
      );
314
 
315
 
316
  -- clk generation
317
  clk     <= not clk     after period_c/2;
318
  clk_udp <= not clk_udp after udp_ip_period_c/2;
319
  rst_n   <= '1'         after 4*period_c;
320
 
321
 
322
  stuupiid : postponed
323
    process (hibi_re_from_duv)
324
    begin
325
      hibi_re <= hibi_re_from_duv;
326
    end process stuupiid;
327
 
328
 
329
  -----------------------------------------------------------------------------
330
  -- Configurations and tx data come from hibi.
331
  -----------------------------------------------------------------------------
332
  hibi_traffic : process
333
  begin  -- process hibi_traffic
334
 
335
    test_tx_id <= -1;
336
    if rst_n = '0' then
337
      wait until rst_n = '1';
338
    end if;
339
 
340
    wait for period_c*4;
341
 
342
 
343
    ---------------------------------------------------------------------------  
344
    for n in 0 to num_of_txs_c-1 loop
345
 
346
      test_tx_id <= n;
347
 
348
      -- Provide addr
349
      hibi_av_to_duv    <= '1';
350
      hibi_empty_to_duv <= '0';
351
      hibi_data_to_duv  <= test_txs_c(n).addr;
352
      wait for period_c;
353
 
354
      if hibi_re = '0' then
355
        wait until hibi_re = '1';
356
        wait for period_c;
357
      end if;
358
 
359
      hibi_av_to_duv <= '0';
360
 
361
      -- Provide all the data
362
      for k in 0 to test_txs_c(n).len-1 loop
363
        hibi_data_to_duv <= test_txs_c(n).data(k);
364
 
365
        wait for period_c;
366
        if hibi_re = '0' then
367
          wait until hibi_re = '1';
368
          wait for period_c;
369
        end if;
370
      end loop;  -- k
371
 
372
      -- Wait before next transfer
373
      hibi_empty_to_duv <= '1';
374
      wait for test_txs_c(n).delay;
375
 
376
    end loop;  -- n       
377
    ---------------------------------------------------------------------------
378
 
379
    wait for period_c*50;
380
 
381
    -- Wait that other processes have finished
382
    if udp_traffic_ready = '0' then
383
      wait until udp_traffic_ready = '1';
384
    end if;
385
 
386
 
387
    report "Simulation ended, manual check required!." severity failure;
388
  end process hibi_traffic;
389
 
390
 
391
 
392
  -----------------------------------------------------------------------------
393
  -- This mimics UDP/IP taking the tx data when it's available
394
  -----------------------------------------------------------------------------
395
  udp_ip_reader : process (clk_udp, rst_n)
396
    variable read_cnt  : integer := 0;
397
    variable read_indx : integer;
398
  begin  -- process udp_ip_reader
399
 
400
    if rst_n = '0' then                 -- asynchronous reset (active low)
401
      tx_re_to_duv <= '0';
402
    elsif clk_udp'event and clk_udp = '1' then  -- rising clock edge
403
 
404
      if tx_data_valid_from_duv = '1' then
405
        tx_re_to_duv <= '1';
406
 
407
      else                              -- es 2012-03-23
408
        -- Tx-ctrl detects rising edge of re, so
409
        -- this cannot be 1 all the time
410
        tx_re_to_duv <= '0';             -- es 2012-03-23        
411
      end if;
412
 
413
      if tx_re_to_duv = '1' and tx_data_valid_from_duv = '1' then
414
        -- check that data correct?
415
        read_cnt := read_cnt + 1;
416
      end if;
417
    end if;
418
  end process udp_ip_reader;
419
 
420
 
421
 
422
 
423
 
424
  -----------------------------------------------------------------------------
425
  -- RX data comes from udo/ip
426
  -----------------------------------------------------------------------------
427
  udp_traffic : process
428
  begin  -- process udp_traffic
429
 
430
    test_rx_id <= -1;
431
 
432
    if rst_n = '0' then
433
      wait until rst_n = '1';
434
    end if;
435
 
436
    wait for period_c*4;
437
 
438
    wait for period_c*250;
439
 
440
 
441
    ---------------------------------------------------------------------------
442
    for n in 0 to num_of_rx_tests_c-1 loop
443
 
444
      test_rx_id <= n;
445
 
446
      -- Provide header
447
      new_rx_to_duv        <= '1';
448
      rx_len_to_duv        <= std_logic_vector(to_unsigned(test_rxs(n).rx_len, tx_len_w_c));
449
      source_ip_to_duv     <= test_rxs(n).source_ip;
450
      source_port_to_duv   <= test_rxs(n).source_port;
451
      dest_port_to_duv     <= test_rxs(n).dest_port;
452
      rx_erroneous_to_duv  <= test_rxs(n).rx_erroneous;
453
      rx_data_to_duv       <= test_rx_data(0);
454
      rx_data_valid_to_duv <= '1';
455
 
456
      wait until rx_re_from_duv = '1';
457
      wait for udp_ip_period_c;
458
 
459
      new_rx_to_duv       <= '0';
460
      rx_len_to_duv       <= (others => 'Z');
461
      source_ip_to_duv    <= (others => 'Z');
462
      source_port_to_duv  <= (others => 'Z');
463
      dest_port_to_duv    <= (others => 'Z');
464
      rx_erroneous_to_duv <= 'Z';
465
 
466
      rx_data_valid_to_duv <= '0';
467
      wait for udp_ip_period_c;
468
 
469
      -- Provide payload data
470
      for k in 0 to (test_rxs(n).rx_len+1)/2 - 2 loop
471
 
472
        rx_data_valid_to_duv <= '1';
473
        rx_data_to_duv       <= test_rx_data((k + 1) mod test_rx_data_amount_c);
474
 
475
        if rx_re_from_duv = '0' then
476
          wait until rx_re_from_duv = '1';
477
        end if;
478
        wait for udp_ip_period_c;
479
        rx_data_valid_to_duv <= '0';
480
        wait for udp_ip_period_c;
481
 
482
      end loop;  -- k
483
 
484
      -- Wait before next incoming transfer
485
      wait for test_rxs(n).delay_before_next;
486
 
487
    end loop;  -- n       
488
    ---------------------------------------------------------------------------
489
 
490
 
491
    wait for period_c*50;
492
 
493
    udp_traffic_ready <= '1';
494
    wait;
495
 
496
  end process udp_traffic;
497
 
498
 
499
 
500
 
501
 
502
 
503
 
504
end tb;

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