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URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.interface/] [udp2hibi/] [1.0/] [udp2hibi.1.0.xml] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu
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        TUT
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        ip.hwp.interface
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        udp2hibi
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        1.0
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        - Interface between a UDP/IP block and the HIBI bus.
12 
- Capable of handling one transmission and one incoming packet at a time
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- UDP2HIBI uses HIBI addresses to separate transfers from different agents
14 
- So all agents must use different addresses when sending to UDP2HIBI
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16
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                        clk
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                        clock input
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                        false
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25
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                                                CLK
28
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                                                        0
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                                                        0
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                                                clk
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                                                        0
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                                                        0
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                        8
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                        little
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                        clk_udp
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                        clock udp input (25MHz)
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                        false
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                                                CLK
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                                                        0
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                                                        0
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                                                clk_udp
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                                                        0
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                                                        0
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                        8
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                        little
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                        hibi_master
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                        HIBI master interface
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                        false
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                                                AV
84
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                                                        0
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                                                        0
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                                                hibi_av_out
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92 
                                                        0
93 
                                                        0
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95
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98
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                                                COMM
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101 
                                                        4
102 
                                                        0
103
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105
106 
                                                hibi_comm_out
107
108 
                                                        4
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                                                        0
110
111
112
113
114
115 
                                                DATA
116
117 
                                                        31
118 
                                                        0
119
120
121
122 
                                                hibi_data_out
123
124 
                                                        31
125 
                                                        0
126
127
128
129
130
131 
                                                RE
132
133 
                                                        0
134 
                                                        0
135
136
137
138 
                                                hibi_re_out
139
140 
                                                        0
141 
                                                        0
142
143
144
145
146
147 
                                                WE
148
149 
                                                        0
150 
                                                        0
151
152
153
154 
                                                hibi_we_out
155
156 
                                                        0
157 
                                                        0
158
159
160
161
162 
                        8
163 
                        little
164
165
166 
                        rst_n
167 
                        active low reset
168
169
170
171 
                        false
172
173
174
175 
                                                RESETn
176
177 
                                                        0
178 
                                                        0
179
180
181
182 
                                                rst_n
183
184 
                                                        0
185 
                                                        0
186
187
188
189
190 
                        8
191 
                        little
192
193
194 
                        udp_ip_rx
195 
                        udp_ip_rx
196
197
198
199 
                        false
200
201
202
203 
                                                source_port_out
204
205 
                                                        15
206 
                                                        0
207
208
209
210 
                                                source_port_in
211
212 
                                                        15
213 
                                                        0
214
215
216
217
218
219 
                                                dest_port_out
220
221 
                                                        15
222 
                                                        0
223
224
225
226 
                                                dest_port_in
227
228 
                                                        15
229 
                                                        0
230
231
232
233
234
235 
                                                source_addr_out
236
237 
                                                        31
238 
                                                        0
239
240
241
242 
                                                source_ip_in
243
244 
                                                        31
245 
                                                        0
246
247
248
249
250
251 
                                                rx_re_in
252
253 
                                                        0
254 
                                                        0
255
256
257
258 
                                                rx_re_out
259
260 
                                                        0
261 
                                                        0
262
263
264
265
266
267 
                                                rx_len_out
268
269 
                                                        10
270 
                                                        0
271
272
273
274 
                                                rx_len_in
275
276 
                                                        10
277 
                                                        0
278
279
280
281
282
283 
                                                rx_erroneous_out
284
285 
                                                        0
286 
                                                        0
287
288
289
290 
                                                rx_erroneous_in
291
292 
                                                        0
293 
                                                        0
294
295
296
297
298
299 
                                                rx_data_valid_out
300
301 
                                                        0
302 
                                                        0
303
304
305
306 
                                                rx_data_valid_in
307
308 
                                                        0
309 
                                                        0
310
311
312
313
314
315 
                                                new_rx_out
316
317 
                                                        0
318 
                                                        0
319
320
321
322 
                                                new_rx_in
323
324 
                                                        0
325 
                                                        0
326
327
328
329
330
331 
                                                rx_data_out
332
333 
                                                        15
334 
                                                        0
335
336
337
338 
                                                rx_data_in
339
340 
                                                        15
341 
                                                        0
342
343
344
345
346
347 
                                                link_up_out
348
349 
                                                        0
350 
                                                        0
351
352
353
354 
                                                eth_link_up_in
355
356 
                                                        0
357 
                                                        0
358
359
360
361
362 
                        8
363 
                        little
364
365
366 
                        udp_ip_tx
367 
                        udp_ip_tx
368
369
370
371 
                        false
372
373
374
375 
                                                tx_data_in
376
377 
                                                        15
378 
                                                        0
379
380
381
382 
                                                tx_data_out
383
384 
                                                        15
385 
                                                        0
386
387
388
389
390
391 
                                                tx_len_in
392
393 
                                                        10
394 
                                                        0
395
396
397
398 
                                                tx_len_out
399
400 
                                                        10
401 
                                                        0
402
403
404
405
406
407 
                                                tx_re_out
408
409 
                                                        0
410 
                                                        0
411
412
413
414 
                                                tx_re_in
415
416 
                                                        0
417 
                                                        0
418
419
420
421
422
423 
                                                tx_data_valid_in
424
425 
                                                        0
426 
                                                        0
427
428
429
430 
                                                tx_data_valid_out
431
432 
                                                        0
433 
                                                        0
434
435
436
437
438
439 
                                                new_tx_in
440
441 
                                                        0
442 
                                                        0
443
444
445
446 
                                                new_tx_out
447
448 
                                                        0
449 
                                                        0
450
451
452
453
454
455 
                                                target_addr_in
456
457 
                                                        31
458 
                                                        0
459
460
461
462 
                                                dest_ip_out
463
464 
                                                        31
465 
                                                        0
466
467
468
469
470
471 
                                                target_port_in
472
473 
                                                        15
474 
                                                        0
475
476
477
478 
                                                dest_port_out
479
480 
                                                        15
481 
                                                        0
482
483
484
485
486
487 
                                                source_port_in
488
489 
                                                        15
490 
                                                        0
491
492
493
494 
                                                source_port_out
495
496 
                                                        15
497 
                                                        0
498
499
500
501
502 
                        8
503 
                        little
504
505
506 
                        hibi_slave
507 
                        HIBI slave interface
508
509
510
511 
                        false
512
513
514
515 
                                                AV
516
517 
                                                        0
518 
                                                        0
519
520
521
522 
                                                hibi_av_in
523
524 
                                                        0
525 
                                                        0
526
527
528
529
530
531 
                                                COMM
532
533 
                                                        4
534 
                                                        0
535
536
537
538 
                                                hibi_comm_in
539
540 
                                                        4
541 
                                                        0
542
543
544
545
546
547 
                                                DATA
548
549 
                                                        31
550 
                                                        0
551
552
553
554 
                                                hibi_data_in
555
556 
                                                        31
557 
                                                        0
558
559
560
561
562
563 
                                                EMPTY
564
565 
                                                        0
566 
                                                        0
567
568
569
570 
                                                hibi_empty_in
571
572 
                                                        0
573 
                                                        0
574
575
576
577
578
579 
                                                FULL
580
581 
                                                        0
582 
                                                        0
583
584
585
586 
                                                hibi_full_in
587
588 
                                                        0
589 
                                                        0
590
591
592
593
594 
                        8
595 
                        little
596
597
598
599
600
601 
                                rtl
602 
                                ::
603
604 
                                        hdlSources
605
606
607
608
609
610 
                                clk
611
612 
                                        in
613
614 
                                                0
615 
                                                0
616
617
618
619 
                                                        std_logic
620 
                                                        IEEE.std_logic_1164.all
621 
                                                        rtl
622
623
624
625
626
627
628 
                                clk_udp
629
630 
                                        in
631
632 
                                                0
633 
                                                0
634
635
636
637 
                                                        std_logic
638 
                                                        IEEE.std_logic_1164.all
639 
                                                        rtl
640
641
642
643
644
645
646 
                                dest_ip_out
647
648 
                                        out
649
650 
                                                31
651 
                                                0
652
653
654
655 
                                                        std_logic_vector
656 
                                                        IEEE.std_logic_1164.all
657 
                                                        rtl
658
659
660
661
662
663
664 
                                dest_port_in
665
666 
                                        in
667
668 
                                                15
669 
                                                0
670
671
672
673 
                                                        std_logic_vector
674 
                                                        IEEE.std_logic_1164.all
675 
                                                        rtl
676
677
678
679
680
681
682 
                                dest_port_out
683
684 
                                        out
685
686 
                                                15
687 
                                                0
688
689
690
691 
                                                        std_logic_vector
692 
                                                        IEEE.std_logic_1164.all
693 
                                                        rtl
694
695
696
697
698
699
700 
                                eth_link_up_in
701
702 
                                        in
703
704 
                                                0
705 
                                                0
706
707
708
709 
                                                        std_logic
710 
                                                        IEEE.std_logic_1164.all
711 
                                                        rtl
712
713
714
715
716
717
718 
                                hibi_av_in
719
720 
                                        in
721
722 
                                                0
723 
                                                0
724
725
726
727 
                                                        std_logic
728 
                                                        IEEE.std_logic_1164.all
729 
                                                        rtl
730
731
732
733
734
735
736 
                                hibi_av_out
737
738 
                                        out
739
740 
                                                0
741 
                                                0
742
743
744
745 
                                                        std_logic
746 
                                                        IEEE.std_logic_1164.all
747 
                                                        rtl
748
749
750
751
752
753
754 
                                hibi_comm_in
755
756 
                                        in
757
758 
                                                4
759 
                                                0
760
761
762
763 
                                                        std_logic_vector
764 
                                                        IEEE.std_logic_1164.all
765 
                                                        rtl
766
767
768
769
770
771
772 
                                hibi_comm_out
773
774 
                                        out
775
776 
                                                4
777 
                                                0
778
779
780
781 
                                                        std_logic_vector
782 
                                                        IEEE.std_logic_1164.all
783 
                                                        rtl
784
785
786
787
788
789
790 
                                hibi_data_in
791
792 
                                        in
793
794 
                                                31
795 
                                                0
796
797
798
799 
                                                        std_logic_vector
800 
                                                        IEEE.std_logic_1164.all
801 
                                                        rtl
802
803
804
805
806
807
808 
                                hibi_data_out
809
810 
                                        out
811
812 
                                                31
813 
                                                0
814
815
816
817 
                                                        std_logic_vector
818 
                                                        IEEE.std_logic_1164.all
819 
                                                        rtl
820
821
822
823
824
825
826 
                                hibi_empty_in
827
828 
                                        in
829
830 
                                                0
831 
                                                0
832
833
834
835 
                                                        std_logic
836 
                                                        IEEE.std_logic_1164.all
837 
                                                        rtl
838
839
840
841
842
843
844 
                                hibi_full_in
845
846 
                                        in
847
848 
                                                0
849 
                                                0
850
851
852
853 
                                                        std_logic
854 
                                                        IEEE.std_logic_1164.all
855 
                                                        rtl
856
857
858
859
860
861
862 
                                hibi_re_out
863
864 
                                        out
865
866 
                                                0
867 
                                                0
868
869
870
871 
                                                        std_logic
872 
                                                        IEEE.std_logic_1164.all
873 
                                                        rtl
874
875
876
877
878
879
880 
                                hibi_we_out
881
882 
                                        out
883
884 
                                                0
885 
                                                0
886
887
888
889 
                                                        std_logic
890 
                                                        IEEE.std_logic_1164.all
891 
                                                        rtl
892
893
894
895
896
897
898 
                                new_rx_in
899
900 
                                        in
901
902 
                                                0
903 
                                                0
904
905
906
907 
                                                        std_logic
908 
                                                        IEEE.std_logic_1164.all
909 
                                                        rtl
910
911
912
913
914
915
916 
                                new_tx_out
917
918 
                                        out
919
920 
                                                0
921 
                                                0
922
923
924
925 
                                                        std_logic
926 
                                                        IEEE.std_logic_1164.all
927 
                                                        rtl
928
929
930
931
932
933
934 
                                rst_n
935
936 
                                        in
937
938 
                                                0
939 
                                                0
940
941
942
943 
                                                        std_logic
944 
                                                        IEEE.std_logic_1164.all
945 
                                                        rtl
946
947
948
949
950
951
952 
                                rx_data_in
953
954 
                                        in
955
956 
                                                15
957 
                                                0
958
959
960
961 
                                                        std_logic_vector
962 
                                                        IEEE.std_logic_1164.all
963 
                                                        rtl
964
965
966
967
968
969
970 
                                rx_data_valid_in
971
972 
                                        in
973
974 
                                                0
975 
                                                0
976
977
978
979 
                                                        std_logic
980 
                                                        IEEE.std_logic_1164.all
981 
                                                        rtl
982
983
984
985
986
987
988 
                                rx_erroneous_in
989
990 
                                        in
991
992 
                                                0
993 
                                                0
994
995
996
997 
                                                        std_logic
998 
                                                        IEEE.std_logic_1164.all
999 
                                                        rtl
1000
1001
1002
1003
1004
1005
1006 
                                rx_len_in
1007
1008 
                                        in
1009
1010 
                                                10
1011 
                                                0
1012
1013
1014
1015 
                                                        std_logic_vector
1016 
                                                        IEEE.std_logic_1164.all
1017 
                                                        rtl
1018
1019
1020
1021
1022
1023
1024 
                                rx_re_out
1025
1026 
                                        out
1027
1028 
                                                0
1029 
                                                0
1030
1031
1032
1033 
                                                        std_logic
1034 
                                                        IEEE.std_logic_1164.all
1035 
                                                        rtl
1036
1037
1038
1039
1040
1041
1042 
                                source_ip_in
1043
1044 
                                        in
1045
1046 
                                                31
1047 
                                                0
1048
1049
1050
1051 
                                                        std_logic_vector
1052 
                                                        IEEE.std_logic_1164.all
1053 
                                                        rtl
1054
1055
1056
1057
1058
1059
1060 
                                source_port_in
1061
1062 
                                        in
1063
1064 
                                                15
1065 
                                                0
1066
1067
1068
1069 
                                                        std_logic_vector
1070 
                                                        IEEE.std_logic_1164.all
1071 
                                                        rtl
1072
1073
1074
1075
1076
1077
1078 
                                source_port_out
1079
1080 
                                        out
1081
1082 
                                                15
1083 
                                                0
1084
1085
1086
1087 
                                                        std_logic_vector
1088 
                                                        IEEE.std_logic_1164.all
1089 
                                                        rtl
1090
1091
1092
1093
1094
1095
1096 
                                tx_data_out
1097
1098 
                                        out
1099
1100 
                                                15
1101 
                                                0
1102
1103
1104
1105 
                                                        std_logic_vector
1106 
                                                        IEEE.std_logic_1164.all
1107 
                                                        rtl
1108
1109
1110
1111
1112
1113
1114 
                                tx_data_valid_out
1115
1116 
                                        out
1117
1118 
                                                0
1119 
                                                0
1120
1121
1122
1123 
                                                        std_logic
1124 
                                                        IEEE.std_logic_1164.all
1125 
                                                        rtl
1126
1127
1128
1129
1130
1131
1132 
                                tx_len_out
1133
1134 
                                        out
1135
1136 
                                                10
1137 
                                                0
1138
1139
1140
1141 
                                                        std_logic_vector
1142 
                                                        IEEE.std_logic_1164.all
1143 
                                                        rtl
1144
1145
1146
1147
1148
1149
1150 
                                tx_re_in
1151
1152 
                                        in
1153
1154 
                                                0
1155 
                                                0
1156
1157
1158
1159 
                                                        std_logic
1160 
                                                        IEEE.std_logic_1164.all
1161 
                                                        rtl
1162
1163
1164
1165
1166
1167
1168
1169
1170 
                                ack_fifo_depth_g
1171 
                                4
1172
1173
1174 
                                frequency_g
1175 
                                50000000
1176
1177
1178 
                                hibi_addr_width_g
1179 
                                32
1180
1181
1182 
                                hibi_comm_width_g
1183 
                                5
1184
1185
1186 
                                hibi_data_width_g
1187 
                                32
1188
1189
1190 
                                hibi_tx_fifo_depth_g
1191 
                                10
1192
1193
1194 
                                receiver_table_size_g
1195 
                                4
1196
1197
1198 
                                rx_multiclk_fifo_depth_g
1199 
                                10
1200
1201
1202 
                                tx_multiclk_fifo_depth_g
1203 
                                10
1204
1205
1206
1207
1208
1209 
                        hdlSources
1210
1211 
                                vhd/udp2hibi_pkg.vhd
1212 
                                vhdlSource
1213 
                                false
1214 
                                udp2hibi
1215
1216
1217 
                                vhd/ctrl_regs.vhd
1218 
                                vhdlSource
1219 
                                false
1220 
                                udp2hibi
1221
1222
1223 
                                vhd/hibi_receiver.vhd
1224 
                                vhdlSource
1225 
                                false
1226 
                                udp2hibi
1227
1228
1229 
                                vhd/hibi_transmitter.vhd
1230 
                                vhdlSource
1231 
                                false
1232 
                                udp2hibi
1233
1234
1235 
                                vhd/rx_ctrl.vhd
1236 
                                vhdlSource
1237 
                                false
1238 
                                udp2hibi
1239
1240
1241 
                                vhd/tx_ctrl.vhd
1242 
                                vhdlSource
1243 
                                false
1244 
                                udp2hibi
1245
1246
1247 
                                vhd/udp2hibi.vhd
1248 
                                vhdlSource
1249 
                                false
1250 
                                udp2hibi
1251
1252
1253
1254 
                        Documentation
1255
1256 
                                doc/HIBI UDP v1.pptx
1257 
                                Documentation
1258 
                                false
1259
1260
1261
1262 
                        testbench
1263
1264 
                                tb/tb_ctrl_regs.vhd
1265 
                                vhdlSource
1266 
                                false
1267
1268
1269 
                                tb/tb_hibi_receiver.vhd
1270 
                                vhdlSource
1271 
                                false
1272
1273
1274 
                                tb/tb_hibi_test.vhd
1275 
                                vhdlSource
1276 
                                false
1277
1278
1279 
                                tb/tb_hibi_transmitter.vhd
1280 
                                vhdlSource
1281 
                                false
1282
1283
1284 
                                tb/tb_rx_ctrl.vhd
1285 
                                vhdlSource
1286 
                                false
1287
1288
1289 
                                tb/tb_tx_ctrl.vhd
1290 
                                vhdlSource
1291 
                                false
1292
1293
1294 
                                tb/tb_udp2hibi.vhd
1295 
                                vhdlSource
1296 
                                false
1297
1298
1299
1300
1301
1302
1303 
                                IP
1304 
                                HW
1305 
                                Mutable
1306
1307
1308
1309

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