1 |
145 |
lanttu |
-------------------------------------------------------------------------------
|
2 |
|
|
-- Title : Supertoplevel
|
3 |
|
|
-- Project : UDP2HIBI
|
4 |
|
|
-------------------------------------------------------------------------------
|
5 |
|
|
-- File : eth_udpip_udp2hibi_top.vhd
|
6 |
|
|
-- Author : Jussi Nieminen
|
7 |
|
|
-- Last update: 2010/01/08
|
8 |
|
|
-------------------------------------------------------------------------------
|
9 |
|
|
-- Description: Combines DM9kA_controller, udp/ip and udp2hibi blocks
|
10 |
|
|
-------------------------------------------------------------------------------
|
11 |
|
|
-- Revisions :
|
12 |
|
|
-- Date Version Author Description
|
13 |
|
|
-- 2009/12/28 1.0 niemin95 Created
|
14 |
|
|
-------------------------------------------------------------------------------
|
15 |
|
|
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
library ieee;
|
19 |
|
|
use ieee.std_logic_1164.all;
|
20 |
|
|
use work.udp2hibi_pkg.all;
|
21 |
|
|
|
22 |
|
|
entity eth_udpip_udp2hibi_top is
|
23 |
|
|
|
24 |
|
|
generic (
|
25 |
|
|
receiver_table_size_g : integer := 2;
|
26 |
|
|
ack_fifo_depth_g : integer := 4;
|
27 |
|
|
tx_multiclk_fifo_depth_g : integer := 5;
|
28 |
|
|
rx_multiclk_fifo_depth_g : integer := 5;
|
29 |
|
|
hibi_tx_fifo_depth_g : integer := 5;
|
30 |
|
|
hibi_data_width_g : integer := 32;
|
31 |
|
|
hibi_addr_width_g : integer := 32;
|
32 |
|
|
hibi_comm_width_g : integer := 3;
|
33 |
|
|
frequency_g : integer := 50000000
|
34 |
|
|
);
|
35 |
|
|
|
36 |
|
|
port (
|
37 |
|
|
clk : in std_logic;
|
38 |
|
|
clk_udp : in std_logic;
|
39 |
|
|
rst_n : in std_logic;
|
40 |
|
|
-- ethernet interface
|
41 |
|
|
eth_clk_out : out std_logic;
|
42 |
|
|
eth_reset_out : out std_logic;
|
43 |
|
|
eth_cmd_out : out std_logic;
|
44 |
|
|
eth_write_out : out std_logic;
|
45 |
|
|
eth_read_out : out std_logic;
|
46 |
|
|
eth_interrupt_in : in std_logic;
|
47 |
|
|
eth_data_inout : inout std_logic_vector( 15 downto 0 );
|
48 |
|
|
eth_chip_sel_out : out std_logic;
|
49 |
|
|
ready_out : out std_logic;
|
50 |
|
|
fatal_error_out : out std_logic;
|
51 |
|
|
-- hibi interface
|
52 |
|
|
hibi_comm_in : in std_logic_vector( hibi_comm_width_g-1 downto 0 );
|
53 |
|
|
hibi_data_in : in std_logic_vector( hibi_data_width_g-1 downto 0 );
|
54 |
|
|
hibi_av_in : in std_logic;
|
55 |
|
|
hibi_empty_in : in std_logic;
|
56 |
|
|
hibi_re_out : out std_logic;
|
57 |
|
|
hibi_comm_out : out std_logic_vector( hibi_comm_width_g-1 downto 0 );
|
58 |
|
|
hibi_data_out : out std_logic_vector( hibi_data_width_g-1 downto 0 );
|
59 |
|
|
hibi_av_out : out std_logic;
|
60 |
|
|
hibi_we_out : out std_logic;
|
61 |
|
|
hibi_full_in : in std_logic
|
62 |
|
|
);
|
63 |
|
|
|
64 |
|
|
end eth_udpip_udp2hibi_top;
|
65 |
|
|
|
66 |
|
|
|
67 |
|
|
|
68 |
|
|
architecture structural of eth_udpip_udp2hibi_top is
|
69 |
|
|
|
70 |
|
|
signal tx_data_udp_eth : std_logic_vector( udp_block_data_w_c-1 downto 0 );
|
71 |
|
|
signal tx_data_valid_udp_eth : std_logic;
|
72 |
|
|
signal tx_re_eth_udp : std_logic;
|
73 |
|
|
signal rx_re_udp_eth : std_logic;
|
74 |
|
|
signal rx_data_eth_udp : std_logic_vector( udp_block_data_w_c-1 downto 0 );
|
75 |
|
|
signal rx_data_valid_eth_udp : std_logic;
|
76 |
|
|
signal target_MAC_udp_eth : std_logic_vector( 47 downto 0 );
|
77 |
|
|
signal new_tx_udp_eth : std_logic;
|
78 |
|
|
signal tx_len_udp_eth : std_logic_vector( tx_len_w_c-1 downto 0 );
|
79 |
|
|
signal tx_frame_type_udp_eth : std_logic_vector( 15 downto 0 );
|
80 |
|
|
signal new_rx_eth_udp : std_logic;
|
81 |
|
|
signal rx_len_eth_udp : std_logic_vector( tx_len_w_c-1 downto 0 );
|
82 |
|
|
signal rx_frame_type_eth_udp : std_logic_vector( 15 downto 0 );
|
83 |
|
|
signal rx_erroneous_eth_udp : std_logic;
|
84 |
|
|
|
85 |
|
|
signal new_tx_udp2hibi_udp : std_logic;
|
86 |
|
|
signal tx_len_udp2hibi_udp : std_logic_vector( tx_len_w_c-1 downto 0 );
|
87 |
|
|
signal target_addr_udp2hibi_udp : std_logic_vector( ip_addr_w_c-1 downto 0 );
|
88 |
|
|
signal target_port_udp2hibi_udp : std_logic_vector( udp_port_w_c-1 downto 0 );
|
89 |
|
|
signal source_port_udp2hibi_udp : std_logic_vector( udp_port_w_c-1 downto 0 );
|
90 |
|
|
signal tx_data_udp2hibi_udp : std_logic_vector( udp_block_data_w_c-1 downto 0 );
|
91 |
|
|
signal tx_data_valid_udp2hibi_udp : std_logic;
|
92 |
|
|
signal tx_re_udp_udp2hibi : std_logic;
|
93 |
|
|
signal new_rx_udp_udp2hibi : std_logic;
|
94 |
|
|
signal rx_data_valid_udp_udp2hibi : std_logic;
|
95 |
|
|
signal rx_data_udp_udp2hibi : std_logic_vector( udp_block_data_w_c-1 downto 0 );
|
96 |
|
|
signal rx_re_udp2hibi_udp : std_logic;
|
97 |
|
|
signal rx_erroneous_udp_udp2hibi : std_logic;
|
98 |
|
|
signal source_addr_udp_udp2hibi : std_logic_vector( ip_addr_w_c-1 downto 0 );
|
99 |
|
|
signal source_port_udp_udp2hibi : std_logic_vector( udp_port_w_c-1 downto 0 );
|
100 |
|
|
signal dest_port_udp_udp2hibi : std_logic_vector( udp_port_w_c-1 downto 0 );
|
101 |
|
|
signal rx_len_udp_udp2hibi : std_logic_vector( tx_len_w_c-1 downto 0 );
|
102 |
|
|
|
103 |
|
|
signal fatal_error_from_eth : std_logic;
|
104 |
|
|
signal rx_error_from_udp : std_logic;
|
105 |
|
|
signal eth_ready : std_logic;
|
106 |
|
|
|
107 |
|
|
-------------------------------------------------------------------------------
|
108 |
|
|
begin -- structural
|
109 |
|
|
-------------------------------------------------------------------------------
|
110 |
|
|
|
111 |
|
|
|
112 |
|
|
eth_controller: entity work.DM9kA_controller
|
113 |
|
|
port map (
|
114 |
|
|
clk => clk_udp,
|
115 |
|
|
rst_n => rst_n,
|
116 |
|
|
eth_clk_out => eth_clk_out,
|
117 |
|
|
eth_reset_out => eth_reset_out,
|
118 |
|
|
eth_cmd_out => eth_cmd_out,
|
119 |
|
|
eth_write_out => eth_write_out,
|
120 |
|
|
eth_read_out => eth_read_out,
|
121 |
|
|
eth_interrupt_in => eth_interrupt_in,
|
122 |
|
|
eth_data_inout => eth_data_inout,
|
123 |
|
|
eth_chip_sel_out => eth_chip_sel_out,
|
124 |
|
|
tx_data_in => tx_data_udp_eth,
|
125 |
|
|
tx_data_valid_in => tx_data_valid_udp_eth,
|
126 |
|
|
tx_re_out => tx_re_eth_udp,
|
127 |
|
|
rx_re_in => rx_re_udp_eth,
|
128 |
|
|
rx_data_out => rx_data_eth_udp,
|
129 |
|
|
rx_data_valid_out => rx_data_valid_eth_udp,
|
130 |
|
|
target_MAC_in => target_MAC_udp_eth,
|
131 |
|
|
new_tx_in => new_tx_udp_eth,
|
132 |
|
|
tx_len_in => tx_len_udp_eth,
|
133 |
|
|
tx_frame_type_in => tx_frame_type_udp_eth,
|
134 |
|
|
new_rx_out => new_rx_eth_udp,
|
135 |
|
|
rx_len_out => rx_len_eth_udp,
|
136 |
|
|
rx_frame_type_out => rx_frame_type_eth_udp,
|
137 |
|
|
rx_erroneous_out => rx_erroneous_eth_udp,
|
138 |
|
|
ready_out => eth_ready,
|
139 |
|
|
fatal_error_out => fatal_error_from_eth
|
140 |
|
|
);
|
141 |
|
|
|
142 |
|
|
ready_out <= eth_ready;
|
143 |
|
|
|
144 |
|
|
|
145 |
|
|
udp_ip_block: entity work.udp_ip
|
146 |
|
|
port map (
|
147 |
|
|
clk => clk_udp,
|
148 |
|
|
rst_n => rst_n,
|
149 |
|
|
new_tx_in => new_tx_udp2hibi_udp,
|
150 |
|
|
tx_len_in => tx_len_udp2hibi_udp,
|
151 |
|
|
target_addr_in => target_addr_udp2hibi_udp,
|
152 |
|
|
target_port_in => target_port_udp2hibi_udp,
|
153 |
|
|
source_port_in => source_port_udp2hibi_udp,
|
154 |
|
|
tx_data_in => tx_data_udp2hibi_udp,
|
155 |
|
|
tx_data_valid_in => tx_data_valid_udp2hibi_udp,
|
156 |
|
|
tx_re_out => tx_re_udp_udp2hibi,
|
157 |
|
|
new_rx_out => new_rx_udp_udp2hibi,
|
158 |
|
|
rx_data_valid_out => rx_data_valid_udp_udp2hibi,
|
159 |
|
|
rx_data_out => rx_data_udp_udp2hibi,
|
160 |
|
|
rx_re_in => rx_re_udp2hibi_udp,
|
161 |
|
|
rx_erroneous_out => rx_erroneous_udp_udp2hibi,
|
162 |
|
|
source_addr_out => source_addr_udp_udp2hibi,
|
163 |
|
|
source_port_out => source_port_udp_udp2hibi,
|
164 |
|
|
dest_port_out => dest_port_udp_udp2hibi,
|
165 |
|
|
rx_len_out => rx_len_udp_udp2hibi,
|
166 |
|
|
tx_data_out => tx_data_udp_eth,
|
167 |
|
|
tx_data_valid_out => tx_data_valid_udp_eth,
|
168 |
|
|
tx_re_in => tx_re_eth_udp,
|
169 |
|
|
target_MAC_out => target_MAC_udp_eth,
|
170 |
|
|
new_tx_out => new_tx_udp_eth,
|
171 |
|
|
tx_len_out => tx_len_udp_eth,
|
172 |
|
|
tx_frame_type_out => tx_frame_type_udp_eth,
|
173 |
|
|
rx_data_in => rx_data_eth_udp,
|
174 |
|
|
rx_data_valid_in => rx_data_valid_eth_udp,
|
175 |
|
|
rx_re_out => rx_re_udp_eth,
|
176 |
|
|
new_rx_in => new_rx_eth_udp,
|
177 |
|
|
rx_len_in => rx_len_eth_udp,
|
178 |
|
|
rx_frame_type_in => rx_frame_type_eth_udp,
|
179 |
|
|
rx_erroneous_in => rx_erroneous_eth_udp,
|
180 |
|
|
rx_error_out => rx_error_from_udp
|
181 |
|
|
);
|
182 |
|
|
|
183 |
|
|
fatal_error_out <= fatal_error_from_eth or rx_error_from_udp;
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
udp2hibi_block: entity work.udp2hibi
|
187 |
|
|
generic map (
|
188 |
|
|
receiver_table_size_g => receiver_table_size_g,
|
189 |
|
|
ack_fifo_depth_g => ack_fifo_depth_g,
|
190 |
|
|
tx_multiclk_fifo_depth_g => tx_multiclk_fifo_depth_g,
|
191 |
|
|
rx_multiclk_fifo_depth_g => rx_multiclk_fifo_depth_g,
|
192 |
|
|
hibi_tx_fifo_depth_g => hibi_tx_fifo_depth_g,
|
193 |
|
|
hibi_data_width_g => hibi_data_width_g,
|
194 |
|
|
hibi_addr_width_g => hibi_addr_width_g,
|
195 |
|
|
hibi_comm_width_g => hibi_comm_width_g,
|
196 |
|
|
frequency_g => frequency_g
|
197 |
|
|
)
|
198 |
|
|
port map (
|
199 |
|
|
clk => clk,
|
200 |
|
|
clk_udp => clk_udp,
|
201 |
|
|
rst_n => rst_n,
|
202 |
|
|
hibi_comm_in => hibi_comm_in,
|
203 |
|
|
hibi_data_in => hibi_data_in,
|
204 |
|
|
hibi_av_in => hibi_av_in,
|
205 |
|
|
hibi_empty_in => hibi_empty_in,
|
206 |
|
|
hibi_re_out => hibi_re_out,
|
207 |
|
|
hibi_comm_out => hibi_comm_out,
|
208 |
|
|
hibi_data_out => hibi_data_out,
|
209 |
|
|
hibi_av_out => hibi_av_out,
|
210 |
|
|
hibi_we_out => hibi_we_out,
|
211 |
|
|
hibi_full_in => hibi_full_in,
|
212 |
|
|
tx_data_out => tx_data_udp2hibi_udp,
|
213 |
|
|
tx_data_valid_out => tx_data_valid_udp2hibi_udp,
|
214 |
|
|
tx_re_in => tx_re_udp_udp2hibi,
|
215 |
|
|
new_tx_out => new_tx_udp2hibi_udp,
|
216 |
|
|
tx_len_out => tx_len_udp2hibi_udp,
|
217 |
|
|
dest_ip_out => target_addr_udp2hibi_udp,
|
218 |
|
|
dest_port_out => target_port_udp2hibi_udp,
|
219 |
|
|
source_port_out => source_port_udp2hibi_udp,
|
220 |
|
|
rx_data_in => rx_data_udp_udp2hibi,
|
221 |
|
|
rx_data_valid_in => rx_data_valid_udp_udp2hibi,
|
222 |
|
|
rx_re_out => rx_re_udp2hibi_udp,
|
223 |
|
|
new_rx_in => new_rx_udp_udp2hibi,
|
224 |
|
|
rx_len_in => rx_len_udp_udp2hibi,
|
225 |
|
|
source_ip_in => source_addr_udp_udp2hibi,
|
226 |
|
|
dest_port_in => dest_port_udp_udp2hibi,
|
227 |
|
|
source_port_in => source_port_udp_udp2hibi,
|
228 |
|
|
rx_erroneous_in => rx_erroneous_udp_udp2hibi,
|
229 |
|
|
eth_link_up_in => eth_ready
|
230 |
|
|
);
|
231 |
|
|
|
232 |
|
|
end structural;
|