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-------------------------------------------------------------------------------
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-- Title : Hibi transmitter
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-- Project : UDP2HIBI
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-------------------------------------------------------------------------------
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-- File : hibi_transmitter.vhd
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-- Author : Jussi Nieminen
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-- Last update: 2012-03-23
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-- Platform :
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-------------------------------------------------------------------------------
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-- Description: Takes care of transmitting packets via HIBI.
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-- Gets data from rx ctrl (which gets them from udp/ip).
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-- Checks parameters fromc ctrl-registers and gives data to hibi
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-- transmitter.
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009/12/21 1.0 niemin95 Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.udp2hibi_pkg.all;
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entity hibi_transmitter is
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generic (
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hibi_data_width_g : integer := 32;
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hibi_addr_width_g : integer := 32;
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hibi_comm_width_g : integer := 5;
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ack_fifo_depth_g : integer := 5
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- to/from HIBI
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hibi_comm_out : out std_logic_vector( hibi_comm_width_g-1 downto 0 );
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hibi_data_out : out std_logic_vector( hibi_data_width_g-1 downto 0 );
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hibi_av_out : out std_logic;
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hibi_we_out : out std_logic;
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hibi_full_in : in std_logic;
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-- from/to rx_ctrl
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send_request_in : in std_logic;
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rx_len_in : in std_logic_vector( tx_len_w_c-1 downto 0 );
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ready_for_tx_out : out std_logic;
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rx_empty_in : in std_logic;
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rx_data_in : in std_logic_vector( hibi_data_width_g-1 downto 0 );
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rx_re_out : out std_logic;
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-- from ctrl_regs
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rx_addr_in : in std_logic_vector( hibi_addr_width_g-1 downto 0 );
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ack_addr_in : in std_logic_vector( hibi_addr_width_g-1 downto 0 );
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send_tx_ack_in : in std_logic;
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send_tx_nack_in : in std_logic;
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send_rx_ack_in : in std_logic;
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send_rx_nack_in : in std_logic
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);
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end hibi_transmitter;
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architecture rtl of hibi_transmitter is
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-- FSM
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type state_type is (normal, send_ack_addr, send_ack, send_data_addr, send_rx_header);
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signal state_r : state_type;
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signal data_from_rx_ctrl : std_logic_vector(hibi_data_width_g-1 downto 0); -- obsolete?
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signal re_to_rx_ctrl : std_logic; -- obsolete?
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signal re_we_r : std_logic;
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signal target_addr_r : std_logic_vector(hibi_addr_width_g-1 downto 0);
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-- fifo is used to store ack requests
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-- ** WARNING! **
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-- The fifo is not infinite (really?), so if some agent decides to send e.g.
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-- 100 tx conf packets in a row, the fifo will simply discard ack/nack
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-- requests that don't fit in.
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component fifo
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generic (
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data_width_g : integer;
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depth_g : integer);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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we_in : in std_logic;
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full_out : out std_logic;
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one_p_out : out std_logic;
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re_in : in std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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empty_out : out std_logic;
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one_d_out : out std_logic);
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end component;
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signal requests_to_ack_fifo : std_logic_vector(3 downto 0);
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signal data_to_ack_fifo : std_logic_vector(hibi_addr_width_g+4-1 downto 0);
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signal we_to_ack_fifo : std_logic;
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signal ack_fifo_re_r : std_logic;
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signal data_from_ack_fifo : std_logic_vector(hibi_addr_width_g+4-1 downto 0);
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signal ack_data : std_logic_vector(3 downto 0);
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signal ack_addr : std_logic_vector(hibi_addr_width_g-1 downto 0);
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signal empty_from_ack_fifo : std_logic;
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signal which_ack_r : std_logic_vector(3 downto 0);
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signal target_addr_valid_r : std_logic;
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signal connect_data_in_out_r : std_logic;
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-- Registers for HIBI
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signal hibi_data_r : std_logic_vector(hibi_data_width_g-1 downto 0);
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signal hibi_we_r : std_logic;
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signal new_rx_r : std_logic;
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signal rx_len_r : std_logic_vector(tx_len_w_c-1 downto 0);
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constant hibi_data_comm_c : std_logic_vector( hibi_comm_width_g-1 downto 0 ) := "00010"; --
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-- command 2 = write
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-------------------------------------------------------------------------------
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begin -- rtl
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-------------------------------------------------------------------------------
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hibi_comm_out <= hibi_data_comm_c;
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requests_to_ack_fifo <= send_tx_ack_in & send_tx_nack_in &
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send_rx_ack_in & send_rx_nack_in;
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data_to_ack_fifo <= requests_to_ack_fifo & ack_addr_in;
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we_to_ack_fifo <= send_tx_ack_in or send_tx_nack_in or send_rx_ack_in or send_rx_nack_in;
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ack_fifo: fifo
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generic map (
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data_width_g => hibi_addr_width_g+4,
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depth_g => ack_fifo_depth_g
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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data_in => data_to_ack_fifo,
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we_in => we_to_ack_fifo,
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full_out => open,
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one_p_out => open,
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re_in => ack_fifo_re_r,
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data_out => data_from_ack_fifo,
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empty_out => empty_from_ack_fifo,
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one_d_out => open
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);
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ack_data <= data_from_ack_fifo( hibi_addr_width_g+4-1 downto hibi_addr_width_g );
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ack_addr <= data_from_ack_fifo( hibi_addr_width_g-1 downto 0 );
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-----------------------------------------------------------------------------
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-- switch output between hibi_data_r and rx_data_in
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-----------------------------------------------------------------------------
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output_mux: process (connect_data_in_out_r, rx_data_in, hibi_data_r,
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re_we_r, rx_empty_in, hibi_we_r)
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begin -- process output_mux
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if connect_data_in_out_r = '1' then
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hibi_data_out <= rx_data_in;
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hibi_we_out <= re_we_r and (not rx_empty_in);
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else
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hibi_data_out <= hibi_data_r;
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hibi_we_out <= hibi_we_r;
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end if;
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end process output_mux;
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rx_re_out <= re_we_r and (not hibi_full_in);
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-----------------------------------------------------------------------------
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--
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-----------------------------------------------------------------------------
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main: process (clk, rst_n)
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begin -- process main
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if rst_n = '0' then -- asynchronous reset (active low)
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state_r <= normal;
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ack_fifo_re_r <= '0';
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re_we_r <= '0';
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target_addr_r <= (others => '0');
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which_ack_r <= (others => '0');
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target_addr_valid_r <= '0';
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connect_data_in_out_r <= '0';
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hibi_we_r <= '0';
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hibi_data_r <= (others => '0');
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new_rx_r <= '0';
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rx_len_r <= (others => '0');
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hibi_av_out <= '0';
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ready_for_tx_out <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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-- default values
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ready_for_tx_out <= '0';
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ack_fifo_re_r <= '0';
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hibi_we_r <= '0';
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hibi_av_out <= '0';
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re_we_r <= '0';
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connect_data_in_out_r <= '0';
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-- state machine
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case state_r is
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-----------------------------------------------------------------------
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when normal =>
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-- normal state means that we are either idle or in the middle of
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-- sending data. We don't have to know which case it is, we just
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-- send all the data we get to the address stored in target_addr_r.
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-- We are ready for new transfers when we are in this state and both,
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-- tx_fifo and ack fifo are empty.
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if rx_empty_in = '1' and empty_from_ack_fifo = '1' and send_request_in = '0' then
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ready_for_tx_out <= '1';
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end if;
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-- if rx_ctrl requests a new transmission
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if send_request_in = '1' then
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target_addr_r <= rx_addr_in;
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state_r <= send_data_addr;
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rx_len_r <= rx_len_in;
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new_rx_r <= '1';
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hibi_av_out <= '1';
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hibi_we_r <= '1';
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hibi_data_r <= rx_addr_in;
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-- else if there is new (n)ack to be sent
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elsif empty_from_ack_fifo = '0' then
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which_ack_r <= ack_data;
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ack_fifo_re_r <= '1';
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-- target address for data is no longer in hibi wrapper's register
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target_addr_valid_r <= '0';
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hibi_av_out <= '1';
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hibi_data_r <= ack_addr;
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hibi_we_r <= '1';
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state_r <= send_ack_addr;
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-- else if there is data to be sent and room where to send it
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elsif rx_empty_in = '0' and hibi_full_in = '0' then
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-- if we have sent an ack/nack in the middle of the transfer, we
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-- have to resend the target address
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if target_addr_valid_r = '0' then
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hibi_av_out <= '1';
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hibi_we_r <= '1';
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hibi_data_r <= target_addr_r;
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state_r <= send_data_addr;
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else
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-- address is valid, just keep on sending data
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re_we_r <= '1';
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connect_data_in_out_r <= '1';
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end if;
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end if;
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-----------------------------------------------------------------------
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when send_ack_addr =>
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hibi_we_r <= '1';
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if hibi_full_in = '0' then
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if which_ack_r(3) = '1' or which_ack_r(1) = '1' then
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-- it's an ack
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hibi_data_r( id_hi_idx_c downto id_lo_idx_c ) <= ack_header_id_c;
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else
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-- a nack
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hibi_data_r( id_hi_idx_c downto id_lo_idx_c ) <= nack_header_id_c;
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end if;
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if which_ack_r(3) = '1' or which_ack_r(2) = '1' then
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-- it's tx (n)ack
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hibi_data_r( id_lo_idx_c-1 ) <= '1';
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else
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-- rx (n)ack
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hibi_data_r( id_lo_idx_c-1 ) <= '0';
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end if;
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hibi_data_r( id_lo_idx_c-2 downto 0 ) <= (others => '0');
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state_r <= send_ack;
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else
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hibi_av_out <= '1';
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end if;
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-----------------------------------------------------------------------
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when send_ack =>
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-- ack is currently being sent. Decide what to do next.
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if hibi_full_in = '0' then
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if empty_from_ack_fifo = '1' and rx_empty_in = '1' then
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-- no more acks and no data, start waiting in normal state
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state_r <= normal;
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elsif empty_from_ack_fifo = '0' then
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-- another ack, send it
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which_ack_r <= ack_data;
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ack_fifo_re_r <= '1';
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hibi_av_out <= '1';
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hibi_data_r <= ack_addr;
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hibi_we_r <= '1';
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state_r <= send_ack_addr;
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else
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-- there's data to be sent, resend the address
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hibi_av_out <= '1';
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hibi_we_r <= '1';
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hibi_data_r <= target_addr_r;
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state_r <= send_data_addr;
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end if;
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else
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hibi_we_r <= '1';
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end if;
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-----------------------------------------------------------------------
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when send_data_addr =>
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-- send receiver address, and after that either send a new rx header
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-- or continue the old rx
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if hibi_full_in = '0' then
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if new_rx_r = '1' then
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-- new rx, send header
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hibi_we_r <= '1';
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hibi_data_r <= (others => '0');
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hibi_data_r(id_hi_idx_c downto id_lo_idx_c) <= rx_data_header_id_c;
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|
hibi_data_r(id_lo_idx_c-1 downto id_lo_idx_c-tx_len_w_c) <= rx_len_r;
|
341 |
|
|
state_r <= send_rx_header;
|
342 |
|
|
new_rx_r <= '0';
|
343 |
|
|
|
344 |
|
|
else
|
345 |
|
|
state_r <= normal;
|
346 |
|
|
-- if possible, start sending
|
347 |
|
|
if rx_empty_in = '0' and hibi_full_in = '0' then
|
348 |
|
|
re_we_r <= '1';
|
349 |
|
|
connect_data_in_out_r <= '1';
|
350 |
|
|
end if;
|
351 |
|
|
end if;
|
352 |
|
|
|
353 |
|
|
target_addr_valid_r <= '1';
|
354 |
|
|
else
|
355 |
|
|
hibi_av_out <= '1';
|
356 |
|
|
hibi_we_r <= '1';
|
357 |
|
|
end if;
|
358 |
|
|
|
359 |
|
|
|
360 |
|
|
-----------------------------------------------------------------------
|
361 |
|
|
when send_rx_header =>
|
362 |
|
|
-- new rx starting, send the header
|
363 |
|
|
|
364 |
|
|
if hibi_full_in = '0' then
|
365 |
|
|
state_r <= normal;
|
366 |
|
|
-- if possible, start sending
|
367 |
|
|
if rx_empty_in = '0' and hibi_full_in = '0' then
|
368 |
|
|
re_we_r <= '1';
|
369 |
|
|
connect_data_in_out_r <= '1';
|
370 |
|
|
end if;
|
371 |
|
|
else
|
372 |
|
|
hibi_we_r <= '1';
|
373 |
|
|
end if;
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
when others => null;
|
377 |
|
|
end case;
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
end if;
|
381 |
|
|
end process main;
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
end rtl;
|