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-------------------------------------------------------------------------------
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-- Title : UDP2HIBI toplevel
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-- Project : UDP2HIBI
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-------------------------------------------------------------------------------
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-- File : udp2hibi.vhd
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-- Author : Jussi Nieminen
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-- Last update: 2012-06-20
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-- Platform :
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-------------------------------------------------------------------------------
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-- Description: Converter that should be placed between HIBI wrapper and
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-- UDP_IP block. This is converter's toplevel entity that
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-- includes 5 sub-blocks.
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--
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-- All blocks wishing to use UDP/IP must first configure
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-- this unit before sending data, or being able to receive.
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-- Only one sender can be active at a time.
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-- Configurations are acknowledged.
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2009/12/15 1.0 niemin95 Created
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-- 2012-03-23 1.0 ege Beautifying and commenting.
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.udp2hibi_pkg.all;
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entity udp2hibi is
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generic (
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receiver_table_size_g : integer := 4;
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ack_fifo_depth_g : integer := 4;
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tx_multiclk_fifo_depth_g : integer := 10;
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rx_multiclk_fifo_depth_g : integer := 10;
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hibi_tx_fifo_depth_g : integer := 10;
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hibi_data_width_g : integer := 32;
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hibi_addr_width_g : integer := 32;
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hibi_comm_width_g : integer := 5;
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frequency_g : integer := 50000000);
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port (
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clk : in std_logic;
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clk_udp : in std_logic;
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rst_n : in std_logic;
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-- ** to/from HIBI **
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-- receiver
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hibi_comm_in : in std_logic_vector( hibi_comm_width_g-1 downto 0 );
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hibi_data_in : in std_logic_vector( hibi_data_width_g-1 downto 0 );
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hibi_av_in : in std_logic;
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hibi_empty_in : in std_logic;
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hibi_re_out : out std_logic;
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-- sender
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hibi_comm_out : out std_logic_vector( hibi_comm_width_g-1 downto 0 );
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hibi_data_out : out std_logic_vector( hibi_data_width_g-1 downto 0 );
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hibi_av_out : out std_logic;
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hibi_we_out : out std_logic;
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hibi_full_in : in std_logic;
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-- ** to/from UDP/IP **
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-- tx
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tx_data_out : out std_logic_vector( udp_block_data_w_c-1 downto 0 );
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tx_data_valid_out : out std_logic;
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tx_re_in : in std_logic;
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new_tx_out : out std_logic;
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tx_len_out : out std_logic_vector( tx_len_w_c-1 downto 0 );
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dest_ip_out : out std_logic_vector( ip_addr_w_c-1 downto 0 );
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dest_port_out : out std_logic_vector( udp_port_w_c-1 downto 0 );
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source_port_out : out std_logic_vector( udp_port_w_c-1 downto 0 );
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-- rx
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rx_data_in : in std_logic_vector( udp_block_data_w_c-1 downto 0 );
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rx_data_valid_in : in std_logic;
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rx_re_out : out std_logic;
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new_rx_in : in std_logic;
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rx_len_in : in std_logic_vector( tx_len_w_c-1 downto 0 );
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source_ip_in : in std_logic_vector( ip_addr_w_c-1 downto 0 );
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dest_port_in : in std_logic_vector( udp_port_w_c-1 downto 0 );
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source_port_in : in std_logic_vector( udp_port_w_c-1 downto 0 );
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rx_erroneous_in : in std_logic;
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-- from eth controller
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eth_link_up_in : in std_logic
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);
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end udp2hibi;
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architecture structural of udp2hibi is
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-- hibi_receiver <-> tx_ctrl
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signal tx_data_receiver_txctrl : std_logic_vector( udp_block_data_w_c-1 downto 0 );
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signal tx_we_receiver_txctrl : std_logic;
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signal tx_full_txctrl_receiver : std_logic;
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signal new_tx_receiver_txctrl : std_logic;
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signal tx_len_receiver_txctrl : std_logic_vector( tx_len_w_c-1 downto 0 );
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signal new_tx_ack_txctrl_receiver : std_logic;
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signal timeout_receiver_txctrl : std_logic_vector( timeout_w_c-1 downto 0 );
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signal timeout_txctrl_receiver : std_logic;
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-- hibi_receiver <-> ctrl_regs
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signal release_lock_receiver_regs : std_logic;
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signal new_tx_conf_receiver_regs : std_logic;
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signal new_rx_conf_receiver_regs : std_logic;
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signal ip_receiver_regs : std_logic_vector( ip_addr_w_c-1 downto 0 );
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signal dest_port_receiver_regs : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal source_port_receiver_regs : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal lock_addr_receiver_regs : std_logic_vector( hibi_addr_width_g-1 downto 0 );
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signal response_addr_receiver_regs : std_logic_vector( hibi_addr_width_g-1 downto 0 );
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signal lock_regs_receiver : std_logic;
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signal lock_addr_regs_receiver : std_logic_vector( hibi_addr_width_g-1 downto 0 );
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-- ctrl_regs <-> tx_ctrl
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signal ip_regs_txctrl : std_logic_vector( ip_addr_w_c-1 downto 0 );
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signal dest_port_regs_txctrl : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal source_port_regs_txctrl : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal timeout_release_txctrl_regs : std_logic;
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-- ctrl_regs <-> rx_ctrl
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signal ip_rxctrl_regs : std_logic_vector( ip_addr_w_c-1 downto 0 );
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signal dest_port_rxctrl_regs : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal source_port_rxctrl_regs : std_logic_vector( udp_port_w_c-1 downto 0 );
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signal rx_addr_valid_regs_rxctrl : std_logic;
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-- ctrl_regs <-> hibi_transmitter
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signal ack_addr_regs_transmitter : std_logic_vector( hibi_addr_width_g-1 downto 0 );
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signal rx_addr_regs_transmitter : std_logic_vector( hibi_addr_width_g-1 downto 0 );
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signal send_tx_ack_regs_transmitter : std_logic;
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signal send_tx_nack_regs_transmitter : std_logic;
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signal send_rx_ack_regs_transmitter : std_logic;
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signal send_rx_nack_regs_transmitter : std_logic;
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-- rx_ctrl <-> hibi_transmitter
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signal send_request_rxctrl_transmitter : std_logic;
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signal rx_len_rxctrl_transmitter : std_logic_vector( tx_len_w_c-1 downto 0 );
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signal ready_for_tx_transmitter_rxctrl : std_logic;
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signal rx_empty_rxctrl_transmitter : std_logic;
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signal rx_data_rxctrl_transmitter : std_logic_vector( hibi_data_width_g-1 downto 0 );
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signal rx_re_transmitter_rxctrl : std_logic;
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-------------------------------------------------------------------------------
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begin -- structural
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-------------------------------------------------------------------------------
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--
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-- +---------------------------------+----------+
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-- | | |
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-- (hibi) ---> hibi receiver --> tx ctrl ---> udp/ip --> eth
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-- | \ / | |
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-- | ctrl regs | |
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-- | / \ | |
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-- (hibi)<--- hibi transmitter --> rx ctrl <--- udp/ip <-- eth
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-- | | |
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-- +---------------------------------+----------+
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--
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-- Gets configurations and data from hibi. Forwards them to ctrl-reg and tx-ctrl
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hibi_receiver_block : entity work.hibi_receiver
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generic map (
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hibi_comm_width_g => hibi_comm_width_g,
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hibi_addr_width_g => hibi_addr_width_g,
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hibi_data_width_g => hibi_data_width_g
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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hibi_comm_in => hibi_comm_in,
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hibi_data_in => hibi_data_in,
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hibi_av_in => hibi_av_in,
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hibi_re_out => hibi_re_out,
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hibi_empty_in => hibi_empty_in,
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tx_data_out => tx_data_receiver_txctrl,
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tx_we_out => tx_we_receiver_txctrl,
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tx_full_in => tx_full_txctrl_receiver,
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new_tx_out => new_tx_receiver_txctrl,
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tx_length_out => tx_len_receiver_txctrl,
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new_tx_ack_in => new_tx_ack_txctrl_receiver,
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timeout_out => timeout_receiver_txctrl,
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timeout_in => timeout_txctrl_receiver,
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release_lock_out => release_lock_receiver_regs,
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new_tx_conf_out => new_tx_conf_receiver_regs,
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new_rx_conf_out => new_rx_conf_receiver_regs,
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ip_out => ip_receiver_regs,
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dest_port_out => dest_port_receiver_regs,
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source_port_out => source_port_receiver_regs,
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lock_addr_out => lock_addr_receiver_regs,
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response_addr_out => response_addr_receiver_regs,
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lock_in => lock_regs_receiver,
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lock_addr_in => lock_addr_regs_receiver
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);
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-- Stores the configurations
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ctrl_regs_block : entity work.ctrl_regs
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generic map (
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receiver_table_size_g => receiver_table_size_g,
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hibi_addr_width_g => hibi_addr_width_g
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)
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port map (
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clk => clk,
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rst_n => rst_n,
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release_lock_in => release_lock_receiver_regs,
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new_tx_conf_in => new_tx_conf_receiver_regs,
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new_rx_conf_in => new_rx_conf_receiver_regs,
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ip_in => ip_receiver_regs,
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dest_port_in => dest_port_receiver_regs,
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source_port_in => source_port_receiver_regs,
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lock_addr_in => lock_addr_receiver_regs,
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response_addr_in => response_addr_receiver_regs,
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lock_out => lock_regs_receiver,
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lock_addr_out => lock_addr_regs_receiver,
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tx_ip_out => ip_regs_txctrl,
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tx_dest_port_out => dest_port_regs_txctrl,
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tx_source_port_out => source_port_regs_txctrl,
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timeout_release_in => timeout_release_txctrl_regs,
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rx_ip_in => ip_rxctrl_regs,
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rx_dest_port_in => dest_port_rxctrl_regs,
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rx_source_port_in => source_port_rxctrl_regs,
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rx_addr_valid_out => rx_addr_valid_regs_rxctrl,
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ack_addr_out => ack_addr_regs_transmitter,
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rx_addr_out => rx_addr_regs_transmitter,
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send_tx_ack_out => send_tx_ack_regs_transmitter,
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send_tx_nack_out => send_tx_nack_regs_transmitter,
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send_rx_ack_out => send_rx_ack_regs_transmitter,
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send_rx_nack_out => send_rx_nack_regs_transmitter,
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eth_link_up_in => eth_link_up_in
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);
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-- Forwads data to ucp/ip
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tx_ctrl_block : entity work.tx_ctrl
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generic map (
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multiclk_fifo_depth_g => tx_multiclk_fifo_depth_g,
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frequency_g => frequency_g
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)
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port map (
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clk => clk,
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clk_udp => clk_udp,
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rst_n => rst_n,
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tx_data_in => tx_data_receiver_txctrl,
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tx_we_in => tx_we_receiver_txctrl,
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tx_full_out => tx_full_txctrl_receiver,
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tx_data_out => tx_data_out,
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tx_data_valid_out => tx_data_valid_out,
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tx_re_in => tx_re_in,
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new_tx_out => new_tx_out,
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tx_len_out => tx_len_out,
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dest_ip_out => dest_ip_out,
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dest_port_out => dest_port_out,
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source_port_out => source_port_out,
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new_tx_in => new_tx_receiver_txctrl,
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tx_len_in => tx_len_receiver_txctrl,
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new_tx_ack_out => new_tx_ack_txctrl_receiver,
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timeout_in => timeout_receiver_txctrl,
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timeout_to_hr_out => timeout_txctrl_receiver,
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tx_ip_in => ip_regs_txctrl,
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tx_dest_port_in => dest_port_regs_txctrl,
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tx_source_port_in => source_port_regs_txctrl,
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timeout_release_out => timeout_release_txctrl_regs
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);
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-- Gets data from udp/ip. Forwards it to hibi-transmitter.
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rx_ctrl_block : entity work.rx_ctrl
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generic map (
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rx_multiclk_fifo_depth_g => rx_multiclk_fifo_depth_g,
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tx_fifo_depth_g => hibi_tx_fifo_depth_g,
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hibi_data_width_g => hibi_data_width_g,
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frequency_g => frequency_g
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)
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port map (
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clk => clk,
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clk_udp => clk_udp,
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rst_n => rst_n,
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rx_data_in => rx_data_in,
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rx_data_valid_in => rx_data_valid_in,
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rx_re_out => rx_re_out,
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new_rx_in => new_rx_in,
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rx_len_in => rx_len_in,
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source_ip_in => source_ip_in,
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dest_port_in => dest_port_in,
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source_port_in => source_port_in,
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rx_erroneous_in => rx_erroneous_in,
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ip_out => ip_rxctrl_regs,
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dest_port_out => dest_port_rxctrl_regs,
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source_port_out => source_port_rxctrl_regs,
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rx_addr_valid_in => rx_addr_valid_regs_rxctrl,
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send_request_out => send_request_rxctrl_transmitter,
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rx_len_out => rx_len_rxctrl_transmitter,
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ready_for_tx_in => ready_for_tx_transmitter_rxctrl,
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rx_empty_out => rx_empty_rxctrl_transmitter,
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rx_data_out => rx_data_rxctrl_transmitter,
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rx_re_in => rx_re_transmitter_rxctrl
|
307 |
|
|
);
|
308 |
|
|
|
309 |
|
|
|
310 |
|
|
-- Gets data from rx-ctrl and writes them to hibi
|
311 |
|
|
hibi_transmitter_block : entity work.hibi_transmitter
|
312 |
|
|
generic map (
|
313 |
|
|
hibi_data_width_g => hibi_data_width_g,
|
314 |
|
|
hibi_addr_width_g => hibi_addr_width_g,
|
315 |
|
|
hibi_comm_width_g => hibi_comm_width_g,
|
316 |
|
|
ack_fifo_depth_g => ack_fifo_depth_g
|
317 |
|
|
)
|
318 |
|
|
port map (
|
319 |
|
|
clk => clk,
|
320 |
|
|
rst_n => rst_n,
|
321 |
|
|
hibi_comm_out => hibi_comm_out,
|
322 |
|
|
hibi_data_out => hibi_data_out,
|
323 |
|
|
hibi_av_out => hibi_av_out,
|
324 |
|
|
hibi_we_out => hibi_we_out,
|
325 |
|
|
hibi_full_in => hibi_full_in,
|
326 |
|
|
|
327 |
|
|
send_request_in => send_request_rxctrl_transmitter,
|
328 |
|
|
rx_len_in => rx_len_rxctrl_transmitter,
|
329 |
|
|
ready_for_tx_out => ready_for_tx_transmitter_rxctrl,
|
330 |
|
|
rx_empty_in => rx_empty_rxctrl_transmitter,
|
331 |
|
|
rx_data_in => rx_data_rxctrl_transmitter,
|
332 |
|
|
rx_re_out => rx_re_transmitter_rxctrl,
|
333 |
|
|
rx_addr_in => rx_addr_regs_transmitter,
|
334 |
|
|
|
335 |
|
|
ack_addr_in => ack_addr_regs_transmitter,
|
336 |
|
|
send_tx_ack_in => send_tx_ack_regs_transmitter,
|
337 |
|
|
send_tx_nack_in => send_tx_nack_regs_transmitter,
|
338 |
|
|
send_rx_ack_in => send_rx_ack_regs_transmitter,
|
339 |
|
|
send_rx_nack_in => send_rx_nack_regs_transmitter
|
340 |
|
|
);
|
341 |
|
|
|
342 |
|
|
|
343 |
|
|
end structural;
|