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lanttu |
-------------------------------------------------------------------------------
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-- Title : UDP/IP and LAN91C111 Controller
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-- Project :
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-------------------------------------------------------------------------------
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-- File : udp_ip_lan91c111.vhd
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-- Author : <alhonena@AHVEN>
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-- Company :
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-- Created : 2011-09-19
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-- Last update: 2011-11-07
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: Direct interface for TX and RX operations on UDP/IP protocol
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-- level with external LAN91C111 chip (e.g. Altera Stratix II S180 dev board)
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-- This toplevel uses a 16-bit mode of LAN91C111 controller!
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-------------------------------------------------------------------------------
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-- Copyright (c) 2011
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2011-09-19 1.0 alhonena Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity udp_ip_lan91c111 is
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generic (
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disable_rx_g : integer := 0;
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disable_arp_g : integer := 0); -- If you disable ARP, you must provide
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-- target MAC address (no_arp_target_MAC_in)
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-- with target IP address (target_addr_in)
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port (
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clk : in std_logic; -- 25 MHz clock to ensure proper timing. LAN91C111 is used asynchronously.
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rst_n : in std_logic;
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-- to/from application
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-- TX
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new_tx_in : in std_logic;
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tx_len_in : in std_logic_vector( 10 downto 0 );
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target_addr_in : in std_logic_vector( 31 downto 0 );
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-- Use this with target_addr_in when disable_arp_g = 1:
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no_arp_target_MAC_in : in std_logic_vector( 47 downto 0 ) := (others => '0');
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target_port_in : in std_logic_vector( 15 downto 0 );
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source_port_in : in std_logic_vector( 15 downto 0 );
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tx_data_in : in std_logic_vector( 15 downto 0 );
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tx_data_valid_in : in std_logic;
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tx_re_out : out std_logic;
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-- RX
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new_rx_out : out std_logic;
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rx_data_valid_out : out std_logic;
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rx_data_out : out std_logic_vector( 15 downto 0 );
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rx_re_in : in std_logic;
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rx_erroneous_out : out std_logic;
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source_addr_out : out std_logic_vector( 31 downto 0 );
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source_port_out : out std_logic_vector( 15 downto 0 );
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dest_port_out : out std_logic_vector( 15 downto 0 );
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rx_len_out : out std_logic_vector( 10 downto 0 );
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rx_error_out : out std_logic; -- this means system error, not error
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-- in data caused by network etc.
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-- Status:
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link_up_out : out std_logic;
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fatal_error_out : out std_logic; -- Something wrong with LAN91C111.
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-- To the external ethernet chip (SMSC LAN91C111)
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eth_data_inout : inout std_logic_vector( 31 downto 0 );
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eth_addr_out : out std_logic_vector( 14 downto 0 ); -- note that they start indexing from 1! A1 on the datasheet goes to eth_addr_out(0).
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eth_interrupt_in : in std_logic;
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eth_read_out : out std_logic;
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eth_write_out : out std_logic;
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eth_nADS_out : out std_logic;
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eth_nAEN_out : out std_logic;
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eth_nBE_out : out std_logic_vector(3 downto 0)
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);
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end udp_ip_lan91c111;
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architecture structural of udp_ip_lan91c111 is
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signal tx_data : std_logic_vector(15 downto 0);
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signal tx_data_valid : std_logic;
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signal tx_re : std_logic;
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signal rx_re : std_logic;
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signal rx_data : std_logic_vector(15 downto 0);
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signal rx_data_valid : std_logic;
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signal target_MAC : std_logic_vector(47 downto 0);
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signal new_tx : std_logic;
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signal tx_len : std_logic_vector(10 downto 0);
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signal tx_frame_type : std_logic_vector(15 downto 0);
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signal new_rx : std_logic;
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signal rx_len : std_logic_vector(10 downto 0);
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signal rx_frame_type : std_logic_vector(15 downto 0);
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signal rx_erroneous : std_logic;
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begin -- structural
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assert not (disable_rx_g = 1 and disable_arp_g = 0) report "RX must be enabled if ARP is enabled" severity failure;
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assert disable_rx_g = 0 or disable_rx_g = 1 report "illegal value of disable_rx_g" severity failure;
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assert disable_arp_g = 0 or disable_arp_g = 1 report "illegal value of disable_arp_g" severity failure;
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rx_disable: if disable_rx_g = 1 generate
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lan91c111_controller_1: entity work.lan91c111_controller
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generic map (
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enable_rx_g => '0',
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interface_width_g => 16)
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port map (
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clk => clk,
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rst_n => rst_n,
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eth_data_inout => eth_data_inout,
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eth_addr_out => eth_addr_out,
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eth_interrupt_in => eth_interrupt_in,
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eth_read_out => eth_read_out,
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eth_write_out => eth_write_out,
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eth_nADS_out => eth_nADS_out,
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eth_nAEN_out => eth_nAEN_out,
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eth_nBE_out => eth_nBE_out,
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tx_data_in => tx_data,
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tx_data_valid_in => tx_data_valid,
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tx_re_out => tx_re,
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rx_re_in => rx_re,
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rx_data_out => rx_data,
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rx_data_valid_out => rx_data_valid,
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target_MAC_in => target_MAC,
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new_tx_in => new_tx,
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tx_len_in => tx_len,
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tx_frame_type_in => tx_frame_type,
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new_rx_out => new_rx,
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rx_len_out => rx_len,
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rx_frame_type_out => rx_frame_type,
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rx_erroneous_out => rx_erroneous,
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ready_out => link_up_out,
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fatal_error_out => fatal_error_out);
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end generate rx_disable;
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rx_enable: if disable_rx_g = 0 generate
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lan91c111_controller_1: entity work.lan91c111_controller
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generic map (
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enable_rx_g => '1',
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interface_width_g => 16)
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port map (
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clk => clk,
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rst_n => rst_n,
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eth_data_inout => eth_data_inout,
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eth_addr_out => eth_addr_out,
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eth_interrupt_in => eth_interrupt_in,
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eth_read_out => eth_read_out,
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eth_write_out => eth_write_out,
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eth_nADS_out => eth_nADS_out,
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eth_nAEN_out => eth_nAEN_out,
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eth_nBE_out => eth_nBE_out,
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tx_data_in => tx_data,
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tx_data_valid_in => tx_data_valid,
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tx_re_out => tx_re,
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rx_re_in => rx_re,
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rx_data_out => rx_data,
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rx_data_valid_out => rx_data_valid,
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target_MAC_in => target_MAC,
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new_tx_in => new_tx,
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tx_len_in => tx_len,
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tx_frame_type_in => tx_frame_type,
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new_rx_out => new_rx,
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rx_len_out => rx_len,
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rx_frame_type_out => rx_frame_type,
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rx_erroneous_out => rx_erroneous,
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ready_out => link_up_out,
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fatal_error_out => fatal_error_out);
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end generate rx_enable;
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udp_ip_1: entity work.udp_ip
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generic map (
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disable_rx_g => disable_rx_g,
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disable_arp_g => disable_arp_g)
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port map (
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clk => clk,
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rst_n => rst_n,
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new_tx_in => new_tx_in,
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tx_len_in => tx_len_in,
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target_addr_in => target_addr_in,
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target_port_in => target_port_in,
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source_port_in => source_port_in,
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tx_data_in => tx_data_in,
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tx_data_valid_in => tx_data_valid_in,
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tx_re_out => tx_re_out,
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new_rx_out => new_rx_out,
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rx_data_valid_out => rx_data_valid_out,
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rx_data_out => rx_data_out,
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rx_re_in => rx_re_in,
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rx_erroneous_out => rx_erroneous_out,
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source_addr_out => source_addr_out,
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source_port_out => source_port_out,
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dest_port_out => dest_port_out,
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rx_len_out => rx_len_out,
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no_arp_target_MAC_in => no_arp_target_MAC_in,
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tx_data_out => tx_data,
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tx_data_valid_out => tx_data_valid,
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tx_re_in => tx_re,
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target_MAC_out => target_MAC,
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new_tx_out => new_tx,
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tx_len_out => tx_len,
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tx_frame_type_out => tx_frame_type,
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rx_data_in => rx_data,
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rx_data_valid_in => rx_data_valid,
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rx_re_out => rx_re,
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new_rx_in => new_rx,
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rx_len_in => rx_len,
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rx_frame_type_in => rx_frame_type,
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rx_erroneous_in => rx_erroneous,
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rx_error_out => rx_error_out);
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end structural;
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