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-- megafunction wizard: %ALTSYNCRAM%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram 

-- ============================================================

-- File Name: conf_ram.vhd

-- Megafunction Name(s):

--                      altsyncram

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version

-- ************************************************************

--Copyright (C) 1991-2005 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions 

--and other software and tools, and its AMPP partner logic       

--functions, and any output files any of the foregoing           

--(including device programming or simulation files), and any    

--associated documentation or information are expressly subject  

--to the terms and conditions of the Altera Program License      

--Subscription Agreement, Altera MegaCore Function License       

--Agreement, or other applicable license agreement, including,   

--without limitation, that your use is for the sole purpose of   

--programming logic devices manufactured by Altera and sold by   

--Altera or its authorized distributors.  Please refer to the    

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.altera_mf_components.all;

ENTITY conf_ram IS

        PORT

        (

                address         : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                clock           : IN STD_LOGIC ;

                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

        );

END conf_ram;

ARCHITECTURE SYN OF conf_ram IS

        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (7 DOWNTO 0);

        COMPONENT altsyncram

        GENERIC (

                operation_mode          : STRING;

                width_a         : NATURAL;

                widthad_a               : NATURAL;

                numwords_a              : NATURAL;

                lpm_type                : STRING;

                width_byteena_a         : NATURAL;

                outdata_reg_a           : STRING;

                outdata_aclr_a          : STRING;

                address_aclr_a          : STRING;

                read_during_write_mode_mixed_ports              : STRING;

                power_up_uninitialized          : STRING;

                init_file               : STRING;

                lpm_hint                : STRING;

                intended_device_family          : STRING

        );

        PORT (

                        clock0  : IN STD_LOGIC ;

                        address_a       : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

                        q_a     : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)

        );

        END COMPONENT;

BEGIN

        q    <= sub_wire0(7 DOWNTO 0);

        altsyncram_component : altsyncram

        GENERIC MAP (

                operation_mode => "ROM",

                width_a => 8,

                widthad_a => 4,

                numwords_a => 16,

                lpm_type => "altsyncram",

                width_byteena_a => 1,

                outdata_reg_a => "CLOCK0",

                outdata_aclr_a => "NONE",

                address_aclr_a => "NONE",

                read_during_write_mode_mixed_ports => "DONT_CARE",

                power_up_uninitialized => "FALSE",

                init_file => "conf_ram.mif",

                lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CONF",

                intended_device_family => "Stratix"

        )

        PORT MAP (

                clock0 => clock,

                address_a => address,

                q_a => sub_wire0

        );

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"

-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"

-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: Clock NUMERIC "0"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"

-- Retrieval info: PRIVATE: REGdata NUMERIC "1"

-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGwren NUMERIC "1"

-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGrren NUMERIC "1"

-- Retrieval info: PRIVATE: REGq NUMERIC "1"

-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"

-- Retrieval info: PRIVATE: CLRq NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: enable NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"

-- Retrieval info: PRIVATE: MIFfilename STRING "conf_ram.mif"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"

-- Retrieval info: PRIVATE: JTAG_ID STRING "CONF"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"

-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"

-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "0"

-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"

-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"

-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"

-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"

-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"

-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

-- Retrieval info: CONSTANT: INIT_FILE STRING "conf_ram.mif"

-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CONF"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"

-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]

-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]

-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0

-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram.bsf TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_inst.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_waveforms.html TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL conf_ram_wave*.jpg FALSE