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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [synch_fifos/] [1.0/] [vhd/] [fifo_casev4a.vhd] - Blame information for rev 145

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1 145 lanttu 
-- Fifo with case version 4:
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-- different from v3:
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-- - using variable data_amount in order to update it right away,
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--   rather than wait util the process ends.
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--
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-- Designer : Ari Kulmala
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--
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-- Variable Data_amount will infer register synthesis! Scary stuff, es 07.11.2003
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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entity fifo is
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  generic (
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    width : integer := 0;
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    depth : integer := 0
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    );
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  port (
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    Clk            : in  std_logic;
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    Rst_n          : in  std_logic;     -- Active low
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    Data_In        : in  std_logic_vector (width-1 downto 0);
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    Write_Enable   : in  std_logic;
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    One_Place_Left : out std_logic;
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    Full           : out std_logic;
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    Data_Out       : out std_logic_vector (width-1 downto 0);
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    Read_Enable    : in  std_logic;
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    Empty          : out std_logic;
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    One_Data_Left  : out std_logic
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    );
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end fifo;
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architecture behavioral of fifo is
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  type reg is array (depth downto 2) of std_logic_vector
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    (width-1 downto 0);
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  signal input_buffer : reg;
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  signal WR : std_logic_vector ( 1 downto 0);
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begin  -- behavioral
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  -- Concurrent assignment
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  WR <= Write_Enable & Read_Enable;
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  process (Clk, rst_n)
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    variable Data_amount : integer range 0 to depth;
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  begin  -- process
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    if rst_n = '0' then                   -- asynchronous reset (active low)
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      --     for i in depth downto 2 loop
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      --       input_buffer(i) <= (others => '0');
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      --     end loop;  -- i
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      --     Data_out          <= (others => '0');
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      Data_Amount       := 0;
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      Empty             <= '1';
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      One_Data_Left     <= '0';
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      One_Place_Left    <= '0';
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      Full              <= '0';
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    elsif Clk'event and Clk = '1' then    -- rising clock edge
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      case WR is
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        when "01" =>
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          -- Read data
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          if Data_amount = 0 then
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            Data_amount := Data_amount;
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          elsif Data_amount = 1 then
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            -- Data_out <= (others => '0');
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            Data_amount := Data_amount-1;
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          else
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            Data_out <= input_buffer(Data_amount);
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            Data_amount := Data_amount-1;
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          end if;
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        when "10" =>
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          -- Write Data
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          if Data_amount = 0 then
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            Data_out            <= Data_In;
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            Data_amount := Data_amount+1;
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          elsif Data_amount = depth then
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            input_buffer        <= input_buffer;
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          else
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            for i in depth-1 downto 2 loop
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              input_buffer(i+1) <= input_buffer(i);
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            end loop;  -- i
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            input_buffer(2)     <= Data_In;
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            Data_amount := Data_amount+1;
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          end if;
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        when "11" =>
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          -- Read and Write concurrently
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          if Data_amount = 0 then
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            -- cannot read if empty
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            Data_out            <= Data_in;
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            Data_Amount := Data_Amount +1;
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          elsif Data_amount = 1 then
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            Data_out            <= Data_In;
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          elsif Data_amount = depth then
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            -- cannot write if full
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            Data_out            <= input_buffer (Data_amount);
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            Data_amount := Data_amount-1;
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          else
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            Data_out            <= input_buffer (Data_amount);
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            for i in depth-1 downto 2 loop
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              input_buffer(i+1) <= input_buffer(i);
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            end loop;  -- i
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            input_buffer(2)      <= Data_In;
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          end if;
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        when others =>                            -- Do nothing
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          input_buffer <= input_buffer;
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          Data_amount := Data_amount;
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      end case;
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      if Data_amount = 0 then
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        Empty          <= '1';
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        One_Place_Left <= '0';
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        One_Data_Left  <= '0';
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        Full           <= '0';
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      elsif Data_amount = 1 then
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        Empty          <= '0';
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        One_Data_Left  <= '1';
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        One_Place_Left <= '0';
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        Full           <= '0';
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      elsif Data_amount = depth-1 then    --one place left
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        Empty          <= '0';
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        One_Place_Left <= '1';
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        One_Data_Left  <= '0';
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        Full           <= '0';
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      elsif Data_amount = depth then      --full
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        Empty          <= '0';
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        One_Place_Left <= '0';
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        One_Data_Left  <= '0';
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        Full           <= '1';
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      else
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        Empty          <= '0';
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        One_Place_Left <= '0';
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        One_Data_Left  <= '0';
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        Full           <= '0';
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      end if;
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    end if; --synchronous
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  end process;
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end behavioral;
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