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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [synch_fifos/] [1.0/] [vhd/] [fifo_casev5.vhd] - Blame information for rev 145

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1 145 lanttu 
-------------------------------------------------------------------------------
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-- File        : fifo_casev5.vhdl
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-- Description : Fifo buffer for hibi interface
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-- Author      : Ari Kulmala
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-- Date        : 10.06.2003
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-- Modified    : 18.06.2003 - Re-wrote the way output control signals are
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--                            assigned
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--
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--
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-- Detailed description:
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-- -Input and Output always from the same register
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--   -> input-buffer is shifted whenever write occurs
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--   -> when read, a mux chooses which value to load to the output next
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--      (the oldest)
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--
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-- !NOTE! isn't tested as one-length FIFO. doesn't probably work. (vector
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-- length (1 downto 2) ...
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--
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-- !NOTE!
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-- * Output is zero when empty.
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_arith.all;
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entity fifo is
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  generic (
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    width : integer := 0;
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    depth : integer := 0);
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  port (
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    Clk            : in  std_logic;
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    Rst_n          : in  std_logic;     -- Active low
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    Data_In        : in  std_logic_vector (width-1 downto 0);
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    Write_Enable   : in  std_logic;
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    One_Place_Left : out std_logic;
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    Full           : out std_logic;
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    Data_Out       : out std_logic_vector (width-1 downto 0);
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    Read_Enable    : in  std_logic;
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    Empty          : out std_logic;
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    One_Data_Left  : out std_logic
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    );
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end fifo;
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architecture behavioral of fifo is
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  -- range is this so that one can use data_amount directly to indexing
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  type reg is array (depth downto 2) of std_logic_vector
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    (width-1 downto 0);
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  signal input_buffer       : reg;
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  -- Registers
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  signal Full_reg           : std_logic;
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  signal Empty_reg          : std_logic;
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  signal One_Data_Left_reg  : std_logic;
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  signal One_Place_Left_reg : std_logic;
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  signal Data_amount        : integer range 0 to depth;
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  signal WR : std_logic_vector ( 1 downto 0);
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begin  -- behavioral
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  -- Continuous assignments
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  -- Assigns register values to outputs
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  Full           <= Full_reg;
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  Empty          <= Empty_reg;
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  One_Data_Left  <= One_Data_Left_reg;
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  One_Place_Left <= One_Place_Left_reg;
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  -- Concurrent assignment
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  WR <= Write_Enable & Read_Enable;
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  process (Clk, rst_n)
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  begin  -- process
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    if rst_n = '0' then                   -- asynchronous reset (active low)
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      for i in depth downto 2 loop
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        input_buffer(i) <= (others => '0');
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      end loop;  -- i
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      Data_out           <= (others => '0');
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      Data_Amount        <= 0;
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      Empty_reg          <= '1';
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      One_Data_Left_reg  <= '0';
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      One_Place_Left_reg <= '0';
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      Full_reg           <= '0';
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    elsif Clk'event and Clk = '1' then    -- rising clock edge
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      case WR is
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        when "01"                        =>
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          -- Read data
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          if Data_amount = 0 then
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            -- empty
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            Data_amount       <= Data_amount;
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            Empty_reg         <= '1';
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            One_Data_Left_reg <= '0';
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          elsif Data_amount = 1 then
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            -- 1 data
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            Data_out          <= (others => '0');
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            Data_amount       <= Data_amount-1;
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            Empty_reg         <= '1';
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            One_Data_Left_reg <= '0';
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          elsif Data_amount = 2 then
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            Data_out          <= input_buffer(Data_amount);
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            Data_amount       <= Data_amount-1;
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            Empty_reg         <= '0';
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            One_Data_Left_reg <= '1';
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          else
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            Data_out          <= input_buffer(Data_amount);
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            Data_amount       <= Data_amount-1;
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            One_Data_Left_reg <= '0';
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            Empty_reg         <= '0';
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          end if;
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          -- Fifo's getting emptier
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          if Data_amount = depth-1 then
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            One_Place_Left_reg <= '0';
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            Full_reg           <= '0';
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          elsif Data_amount = depth then
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            One_Place_Left_reg <= '1';
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            Full_reg           <= '0';
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          else
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            One_Place_Left_reg <= '0';
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            Full_reg           <= '0';
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          end if;
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        when "10" =>
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          -- Write Data
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          if Data_amount = 0 then
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            Data_out            <= Data_In;
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            Data_amount         <= Data_amount+1;
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          elsif Data_amount = depth then
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            input_buffer        <= input_buffer;
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          else
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            for i in depth-1 downto 2 loop
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              input_buffer(i+1) <= input_buffer(i);
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            end loop;  -- i
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            input_buffer(2)     <= Data_In;
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            Data_amount         <= Data_amount+1;
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          end if;
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          -- define the values for output control signals
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          if Data_amount = 0 then
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '1';
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            Full_reg           <= '0';
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            One_Place_Left_reg <= '0';
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          elsif Data_amount = 1 then
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '0';
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            Full_reg           <= '0';
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            One_Place_Left_reg <= '0';
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          elsif Data_amount = depth-2 then
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '0';
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            Full_reg           <= '0';
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            One_Place_Left_reg <= '1';
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          elsif Data_amount = depth-1 then
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '0';
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            Full_reg           <= '1';
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            One_Place_Left_reg <= '0';
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          else
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            Empty_reg          <= Empty_reg;
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            One_Data_Left_reg  <= One_Data_Left_reg;
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            Full_reg           <= Full_reg;
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            One_Place_Left_reg <= One_Place_Left_reg;
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          end if;
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        when "11" =>
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          -- Read and Write concurrently
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          if Data_amount = 0 then
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            -- can only write
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            Data_out           <= Data_in;
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '1';
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            Full_reg           <= '0';
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            One_Place_Left_reg <= '0';
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            Data_amount <= Data_amount+1;
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          elsif Data_amount = 1 then
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            Data_out           <= Data_In;
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            Empty_reg          <= '0';
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            One_Data_Left_reg  <= '1';
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            Full_reg           <= '0';
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            One_Place_Left_reg <= '0';
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          elsif Data_amount = depth then
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            -- cannot write if full, just read
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            Data_out            <= input_buffer (Data_amount);
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            Data_amount         <= Data_amount-1;
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            Empty_reg           <= '0';
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            One_Data_Left_reg   <= '0';
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            Full_reg            <= '0';
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            One_Place_Left_reg  <= '1';
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          else
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            Data_out            <= input_buffer (Data_amount);
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            for i in depth-1 downto 2 loop
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              input_buffer(i+1) <= input_buffer(i);
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            end loop;  -- i
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            input_buffer(2)     <= Data_In;
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            Empty_reg           <= Empty_reg;
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            One_Data_Left_reg   <= One_Data_Left_reg;
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            Full_reg            <= Full_reg;
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            One_Place_Left_reg  <= One_Place_Left_reg;
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          end if;
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        when others =>
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          -- Do nothing, write and read low
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          input_buffer       <= input_buffer;
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          Data_amount        <= Data_amount;
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          Empty_reg          <= Empty_reg;
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          One_Data_Left_reg  <= One_Data_Left_reg;
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          Full_reg           <= Full_reg;
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          One_Place_Left_reg <= One_Place_Left_reg;
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      end case;
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    end if; --synchronous
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  end process;
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end behavioral;
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