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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [synch_fifos/] [1.0/] [vhd/] [fifo_im_case.vhd] - Blame information for rev 145

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1 145 lanttu 
-------------------------------------------------------------------------------
2 
-- File        : fifo_im_case.vhdl
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-- Description : Fifo buffer for hibi interface
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-- Author      : Erno Salminen
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-- Date        : 29.04.2002
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-- Modified    : 30.04.2002 Vesa Lahtinen Optimized for synthesis
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--
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--              02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer
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--                      smaller and faster implementation
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--              Effect on synthesis is uncertain :
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--              small fifos seem to gets smaller and faster, but big fifos
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--              get bigger and slower. Strange.
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--
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--              ?.06.03 AK - uses "case" instead of "if" in main process.
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--                        (makes it concurrent rather than sequential)
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity fifo is
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  generic (
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    width : integer := 0;
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    depth : integer := 0);
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  port (
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    Clk            : in  std_logic;
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    Rst_n          : in  std_logic;
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    Data_In        : in  std_logic_vector (width-1 downto 0);
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    Write_Enable   : in  std_logic;
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    One_Place_Left : out std_logic;
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    Full           : out std_logic;
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    Data_Out       : out std_logic_vector (width-1 downto 0);
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    Read_Enable    : in  std_logic;
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    Empty          : out std_logic;
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    One_Data_Left  : out std_logic
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    );
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end fifo;
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architecture behavioral of fifo is
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  type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0);
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  signal Fifo_Buffer : data_array;
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  -- Registers
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  signal Full_reg           : std_logic;
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  signal Empty_reg          : std_logic;
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  signal One_Data_Left_reg  : std_logic;
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  signal One_Place_Left_reg : std_logic;
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  --signal Data_Amount        : std_logic_vector (depth-1 downto 0);
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  signal Data_Amount        : integer range 0 to depth-1;
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  signal WR : std_logic_vector ( 1 downto 0);
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58 
 
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begin  -- in_mux
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  -- Continuous assignments
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  -- Assigns register values to outputs
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  Full           <= Full_reg;
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  Empty          <= Empty_reg;
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  One_Data_Left  <= One_Data_Left_reg;
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  One_Place_Left <= One_Place_Left_reg;
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  Data_Out       <= Fifo_Buffer (0);
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  -- Note! There is some old value in data output when fifo is empty.
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70 
  WR <= Write_Enable & Read_Enable;
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72 
 
73 
Main : process (Clk, Rst_n)
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begin  -- process Main
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  if Rst_n = '0' then                   -- asynchronous reset (active low)
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    -- Reset all registers
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    -- Fifo is empty at first
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    Full_reg           <= '0';
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    Empty_reg          <= '1';
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    One_Data_Left_reg  <= '0';
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    Data_Amount        <= 0;
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    if depth =1 then                    -- 30.07
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      One_Place_Left_reg <= '1';
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    else
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      One_Place_Left_reg <= '0';
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    end if;
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    for i in 0 to depth-1 loop
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      Fifo_Buffer (i)  <= (others => '0');
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    end loop;  -- i
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94 
  elsif Clk'event and Clk = '1' then    -- rising clock edge
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96 
 
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    -- 1) Write data to fifo
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--    if Write_Enable = '1' and Read_Enable = '0' then
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    case WR is
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      when  "10" =>
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      if Full_reg = '0' then
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        Empty_reg                 <= '0';
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        Data_Amount               <= Data_Amount +1;
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        Fifo_Buffer               <= Fifo_Buffer;  --02.06
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        Fifo_Buffer (Data_Amount) <= Data_In;
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        -- Check if the fifo is getting full
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        if Data_Amount + 2 = depth then
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          Full_reg           <= '0';
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          One_Place_Left_reg <= '1';
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        elsif Data_Amount +1 = depth then
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          Full_reg           <= '1';
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          One_Place_Left_reg <= '0';
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        else
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          Full_reg           <= '0';
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          One_Place_Left_reg <= '0';
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        end if;
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        -- If fifo was empty, it has now one data
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        if Empty_reg = '1' then
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          One_Data_Left_reg <= '1';
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        else
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          One_Data_Left_reg <= '0';
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        end if;
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      else
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        Full_reg           <= Full_reg;
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        Empty_reg          <= Empty_reg;
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        Fifo_Buffer        <= Fifo_Buffer;
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        Data_Amount        <= Data_Amount;
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        One_Data_Left_reg  <= One_Data_Left_reg;
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        One_Place_Left_reg <= One_Place_Left_reg;
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      end if;
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    -- 2) Read data from fifo
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--    elsif Write_Enable = '0' and Read_Enable = '1' then
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      when "01" =>
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      if Empty_reg = '0' then
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        -- Shiftaus
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        Fifo_Buffer               <= Fifo_Buffer;  --02.06
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        for i in 0 to depth-2 loop
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          Fifo_Buffer (i) <= Fifo_Buffer (i+1);
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        end loop;  -- i
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        Full_reg    <= '0';
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        Data_Amount <= Data_Amount -1;
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        -- Debug
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        -- Fifo_Buffer (out_ptr) <= (others => '1');
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158 
 
159 
 
160 
 
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        -- Check if the fifo is getting empty
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        if Data_Amount = 2 then
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          Empty_reg         <= '0';
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          One_data_Left_reg <= '1';
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        elsif Data_Amount = 1 then
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          Empty_reg         <= '1';
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          One_Data_Left_reg <= '0';
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        else
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          Empty_reg         <= '0';
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          One_Data_Left_reg <= '0';
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        end if;
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        -- If fifo was full, it is no more
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        if Full_reg = '1' then
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          One_Place_Left_reg <= '1';
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        else
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          One_Place_Left_reg <= '0';
178 
        end if;
179 
 
180 
      else
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        Full_reg           <= Full_reg;
182 
        Empty_reg          <= Empty_reg;
183 
        Fifo_Buffer        <= Fifo_Buffer;
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        Data_Amount        <= Data_Amount;
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        One_Data_Left_reg  <= One_Data_Left_reg;
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        One_Place_Left_reg <= One_Place_Left_reg;
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      end if;
188 
 
189 
 
190 
    -- 3) Write and read at the same time
191 
--    elsif Write_Enable = '1' and Read_Enable = '1' then
192 
 
193 
      when "11" =>
194 
 
195 
      if Full_reg = '0' and Empty_reg = '0' then
196 
        Full_reg           <= '0';
197 
        Empty_reg          <= '0';
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        Data_Amount        <= Data_Amount;
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        One_Data_Left_reg  <= One_Data_Left_reg;
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        One_Place_Left_reg <= One_Place_Left_reg;
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        Fifo_Buffer               <= Fifo_Buffer;  --02.06
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        -- Shiftaus
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        for i in 0 to depth-2 loop
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          Fifo_Buffer (i) <= Fifo_Buffer (i+1);
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        end loop;  -- i
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        Fifo_Buffer (Data_Amount-1)  <= Data_In;  --vai amount-1 ?? koska pitaa
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                                                --shiftata samalla
209 
 
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        -- Fifo_Buffer (out_ptr) <= (others => '1');  --debug
211 
 
212 
 
213 
      elsif Full_reg = '1' and Empty_reg = '0' then
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        -- Fifo is full, only reading is possible
215 
 
216 
        Full_reg              <= '0';
217 
        One_Place_Left_reg    <= '1';
218 
        --Fifo_Buffer (out_ptr) <= (others => '1');  -- Debug
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        Data_Amount           <= Data_Amount -1;
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221 
        Fifo_Buffer               <= Fifo_Buffer;  --02.06
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        -- Shiftaus
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        for i in 0 to depth-2 loop
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          Fifo_Buffer (i) <= Fifo_Buffer (i+1);
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        end loop;  -- i
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227 
        -- Check if the fifo is getting empty
228 
        if Data_Amount = 2 then
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          Empty_reg         <= '0';
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          One_data_Left_reg <= '1';
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        elsif Data_Amount = 1 then
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          Empty_reg         <= '1';
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          One_Data_Left_reg <= '0';
234 
        else
235 
          Empty_reg         <= '0';
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          One_Data_Left_reg <= '0';
237 
        end if;
238 
 
239 
 
240 
      elsif Full_reg = '0' and Empty_reg = '1' then
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        -- Fifo is empty, only writing is possible
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        Empty_reg                 <= '0';
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        One_Data_Left_reg         <= '1';
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        Fifo_Buffer               <= Fifo_Buffer;  --02.06
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        Fifo_Buffer (Data_Amount) <= Data_In;  --Data_Amount =0
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        Data_Amount               <= Data_Amount +1;
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248 
        -- Check if the fifo is getting full
249 
        if Data_Amount + 2 = depth then
250 
          Full_reg           <= '0';
251 
          One_Place_Left_reg <= '1';
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        elsif Data_Amount +1 = depth then
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          Full_reg           <= '1';
254 
          One_Place_Left_reg <= '0';
255 
        else
256 
          Full_reg           <= '0';
257 
          One_Place_Left_reg <= '0';
258 
        end if;
259 
 
260 
 
261 
      else
262 
        -- Fifo is full and empty at the same time => impossible
263 
        Full_reg           <= Full_reg;
264 
        Empty_reg          <= Empty_reg;
265 
        Fifo_Buffer        <= Fifo_Buffer;
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        Data_Amount        <= Data_Amount;
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        One_Data_Left_reg  <= One_Data_Left_reg;
268 
        One_Place_Left_reg <= One_Place_Left_reg;
269 
      end if;                           --Full_reg & Empty_reg
270 
 
271 
 
272 
    -- 4) Do nothing, fifo remains idle
273 
--    else
274 
 
275 
      when others =>
276 
      Full_reg           <= Full_reg;
277 
      Empty_reg          <= Empty_reg;
278 
      Fifo_Buffer        <= Fifo_Buffer;
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      Data_Amount        <= Data_Amount;
280 
      One_Data_Left_reg  <= One_Data_Left_reg;
281 
      One_Place_Left_reg <= One_Place_Left_reg;
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    end case;
283 
 
284 
  end if;
285 
end process Main;
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end behavioral;

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