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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [synch_fifos/] [1.0/] [vhd/] [fifo_iom.vhdl] - Blame information for rev 145

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-------------------------------------------------------------------------------
-- File        : fifo_iom.vhdl
-- Description : Fifo buffer for hibi interface.
--               Uses pointers and muxes for input and output.
--
-- Author      : Erno Salminen
-- Date        : 29.04.2002
-- Modified    : 30.04.2002 Vesa Lahtinen Optimized for synthesis
--
--              02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer
--              Effect on synthesis is uncertain :
--              small fifos seem to gets smaller and faster, but big fifos
--              get bigger and slower. Strange.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity fifo is
 
 
  generic (
    width : integer := 0;
    depth : integer := 0);
 
  port (
    Clk            : in  std_logic;
    Rst_n          : in  std_logic;
    Data_In        : in  std_logic_vector (width-1 downto 0);
    Write_Enable   : in  std_logic;
    One_Place_Left : out std_logic;
    Full           : out std_logic;
    Data_Out       : out std_logic_vector (width-1 downto 0);
    Read_Enable    : in  std_logic;
    Empty          : out std_logic;
    One_Data_Left  : out std_logic
    );
 
end fifo;
 
architecture inout_mux of fifo is
 
  type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0);
  signal Fifo_Buffer : data_array;
 
  signal in_ptr  : integer range 0 to depth-1;
  signal out_ptr : integer range 0 to depth-1;
 
  -- Registers
  signal Full_reg           : std_logic;
  signal Empty_reg          : std_logic;
  signal One_Data_Left_reg  : std_logic;
  signal One_Place_Left_reg : std_logic;
  --signal Data_Amount        : std_logic_vector (depth-1 downto 0);
  signal Data_Amount        : integer range 0 to depth-1;
 
 
begin  -- inout_mux
 
  -- Continuous assignments
  -- Assigns register values to outputs
  Full           <= Full_reg;
  Empty          <= Empty_reg;
  One_Data_Left  <= One_Data_Left_reg;
  One_Place_Left <= One_Place_Left_reg;
  Data_Out       <= Fifo_Buffer (out_ptr);
  -- Note! There is some old value in data output when fifo is empty.
 
 
Main : process (Clk, Rst_n)
begin  -- process Main
  if Rst_n = '0' then                   -- asynchronous reset (active low)
 
    -- Reset all registers
    -- Fifo is empty at first
    Full_reg           <= '0';
    Empty_reg          <= '1';
    One_Data_Left_reg  <= '0';
    in_ptr             <= 0;
    out_ptr            <= 0;
    Data_Amount        <= 0; --(others => '0');
 
    if depth =1 then                    -- 30.07
      One_Place_Left_reg <= '1';
    else
      One_Place_Left_reg <= '0';
    end if;
 
    for i in 0 to depth-1 loop
      Fifo_Buffer (i)  <= (others => '0');
    end loop;  -- i
 
  elsif Clk'event and Clk = '1' then    -- rising clock edge
 
 
    -- 1) Write data to fifo
    if Write_Enable = '1' and Read_Enable = '0' then
 
      if Full_reg = '0' then
        Empty_reg            <= '0';
        if (in_ptr = (depth-1)) then
          in_ptr             <= 0;
        else
          in_ptr             <= in_ptr + 1;
        end if;
        out_ptr              <= out_ptr;
        Data_Amount          <= Data_Amount +1;
        Fifo_Buffer          <= Fifo_Buffer;  --02.06
        Fifo_Buffer (in_ptr) <= Data_In;
 
        -- Check if the fifo is getting full
        if Data_Amount + 2 = depth then
          Full_reg           <= '0';
          One_Place_Left_reg <= '1';
        elsif Data_Amount +1 = depth then
          Full_reg           <= '1';
          One_Place_Left_reg <= '0';
        else
          Full_reg           <= '0';
          One_Place_Left_reg <= '0';
        end if;
 
        -- If fifo was empty, it has now one data 
        if Empty_reg = '1' then
          One_Data_Left_reg <= '1';
        else
          One_Data_Left_reg <= '0';
        end if;
 
      else
        in_ptr             <= in_ptr;
        out_ptr            <= out_ptr;
        Full_reg           <= Full_reg;
        Empty_reg          <= Empty_reg;
        Fifo_Buffer        <= Fifo_Buffer;
        Data_Amount        <= Data_Amount;
        One_Data_Left_reg  <= One_Data_Left_reg;
        One_Place_Left_reg <= One_Place_Left_reg;
      end if;
 
 
    -- 2) Read data from fifo  
    elsif Write_Enable = '0' and Read_Enable = '1' then
 
      if Empty_reg = '0' then
        in_ptr      <= in_ptr;
        if (out_ptr = (depth-1)) then
          out_ptr   <= 0;
        else
          out_ptr   <= out_ptr + 1;
        end if;
        Full_reg    <= '0';
        Data_Amount <= Data_Amount -1;
        Fifo_Buffer <= Fifo_Buffer;     --02.06
 
        -- Debug
        -- Fifo_Buffer (out_ptr) <= (others => '1');
 
        -- Check if the fifo is getting empty
        if Data_Amount = 2 then
          Empty_reg         <= '0';
          One_data_Left_reg <= '1';
        elsif Data_Amount = 1 then
          Empty_reg         <= '1';
          One_Data_Left_reg <= '0';
        else
          Empty_reg         <= '0';
          One_Data_Left_reg <= '0';
        end if;
 
        -- If fifo was full, it is no more 
        if Full_reg = '1' then
          One_Place_Left_reg <= '1';
        else
          One_Place_Left_reg <= '0';
        end if;
 
      else
        in_ptr             <= in_ptr;
        out_ptr            <= out_ptr;
        Full_reg           <= Full_reg;
        Empty_reg          <= Empty_reg;
        Fifo_Buffer        <= Fifo_Buffer;
        Data_Amount        <= Data_Amount;
        One_Data_Left_reg  <= One_Data_Left_reg;
        One_Place_Left_reg <= One_Place_Left_reg;
      end if;
 
 
    -- 3) Write and read at the same time  
    elsif Write_Enable = '1' and Read_Enable = '1' then
 
 
      if Full_reg = '0' and Empty_reg = '0' then
        if (in_ptr = (depth-1)) then
          in_ptr <= 0;
        else
          in_ptr <= in_ptr + 1;
        end if;
        if (out_ptr = (depth-1)) then
          out_ptr <= 0;
        else
          out_ptr <= out_ptr + 1;
        end if;
        Full_reg           <= '0';
        Empty_reg          <= '0';
        Data_Amount        <= Data_Amount;
        One_Data_Left_reg  <= One_Data_Left_reg;
        One_Place_Left_reg <= One_Place_Left_reg;
 
        Fifo_Buffer          <= Fifo_Buffer;          --02.06
        Fifo_Buffer (in_ptr) <= Data_In;
        -- Fifo_Buffer (out_ptr) <= (others => '1');  --debug
 
 
      elsif Full_reg = '1' and Empty_reg = '0' then
        -- Fifo is full, only reading is possible
        in_ptr             <= in_ptr;
        if (out_ptr = (depth-1)) then
          out_ptr          <= 0;
        else
          out_ptr          <= out_ptr + 1;
        end if;
        Full_reg           <= '0';
        One_Place_Left_reg <= '1';
        Fifo_Buffer        <= Fifo_Buffer;           --02.06
        --Fifo_Buffer (out_ptr) <= (others => '1');  -- Debug
        Data_Amount        <= Data_Amount -1;
 
        -- Check if the fifo is getting empty
        if Data_Amount = 2 then
          Empty_reg         <= '0';
          One_data_Left_reg <= '1';
        elsif Data_Amount = 1 then
          Empty_reg         <= '1';
          One_Data_Left_reg <= '0';
        else
          Empty_reg         <= '0';
          One_Data_Left_reg <= '0';
        end if;
 
 
      elsif Full_reg = '0' and Empty_reg = '1' then
        -- Fifo is empty, only writing is possible
        if (in_ptr = (depth-1)) then
          in_ptr             <= 0;
        else
          in_ptr             <= in_ptr + 1;
        end if;
        out_ptr              <= out_ptr;
        Empty_reg            <= '0';
        One_Data_Left_reg    <= '1';
        Fifo_Buffer          <= Fifo_Buffer;  --02.06
        Fifo_Buffer (in_ptr) <= Data_In;
        Data_Amount          <= Data_Amount +1;
 
        -- Check if the fifo is getting full
        if Data_Amount + 2 = depth then
          Full_reg           <= '0';
          One_Place_Left_reg <= '1';
        elsif Data_Amount +1 = depth then
          Full_reg           <= '1';
          One_Place_Left_reg <= '0';
        else
          Full_reg           <= '0';
          One_Place_Left_reg <= '0';
        end if;
 
 
      -- 4) Do nothing, fifo remains idle 
      else
 
        in_ptr             <= in_ptr;
        out_ptr            <= out_ptr;
        Full_reg           <= Full_reg;
        Empty_reg          <= Empty_reg;
        Fifo_Buffer        <= Fifo_Buffer;
        Data_Amount        <= Data_Amount;
        One_Data_Left_reg  <= One_Data_Left_reg;
        One_Place_Left_reg <= One_Place_Left_reg;
      end if;
 
    else
      -- Fifo is idle
      in_ptr             <= in_ptr;
      out_ptr            <= out_ptr;
      Full_reg           <= Full_reg;
      Empty_reg          <= Empty_reg;
      Fifo_Buffer        <= Fifo_Buffer;
      Data_Amount        <= Data_Amount;
      One_Data_Left_reg  <= One_Data_Left_reg;
      One_Place_Left_reg <= One_Place_Left_reg;
    end if;
 
  end if;
end process Main;
 
end inout_mux;

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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [fifos/] [synch_fifos/] [1.0/] [vhd/] [fifo_iom.vhdl] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu	`-------------------------------------------------------------------------------`
2			`-- File : fifo_iom.vhdl`
3			`-- Description : Fifo buffer for hibi interface.`
4			`-- Uses pointers and muxes for input and output.`
5			`--`
6			`-- Author : Erno Salminen`
7			`-- Date : 29.04.2002`
8			`-- Modified : 30.04.2002 Vesa Lahtinen Optimized for synthesis`
9			`--`
10			`-- 02.06 ES: default assignment Fifo_Buffer <= Fifo_Buffer`
11			`-- Effect on synthesis is uncertain :`
12			`-- small fifos seem to gets smaller and faster, but big fifos`
13			`-- get bigger and slower. Strange.`
14			`-------------------------------------------------------------------------------`
15			`library ieee;`
16			`use ieee.std_logic_1164.all;`
17			`use ieee.std_logic_arith.all;`
18			`use ieee.std_logic_unsigned.all;`
19
20			`entity fifo is`
21
22
23			`generic (`
24			`width : integer := 0;`
25			`depth : integer := 0);`
26
27			`port (`
28			`Clk : in std_logic;`
29			`Rst_n : in std_logic;`
30			`Data_In : in std_logic_vector (width-1 downto 0);`
31			`Write_Enable : in std_logic;`
32			`One_Place_Left : out std_logic;`
33			`Full : out std_logic;`
34			`Data_Out : out std_logic_vector (width-1 downto 0);`
35			`Read_Enable : in std_logic;`
36			`Empty : out std_logic;`
37			`One_Data_Left : out std_logic`
38			`);`
39
40			`end fifo;`
41
42			`architecture inout_mux of fifo is`
43
44			`type data_array is array (depth-1 downto 0) of std_logic_vector (width-1 downto 0);`
45			`signal Fifo_Buffer : data_array;`
46
47			`signal in_ptr : integer range 0 to depth-1;`
48			`signal out_ptr : integer range 0 to depth-1;`
49
50			`-- Registers`
51			`signal Full_reg : std_logic;`
52			`signal Empty_reg : std_logic;`
53			`signal One_Data_Left_reg : std_logic;`
54			`signal One_Place_Left_reg : std_logic;`
55			`--signal Data_Amount : std_logic_vector (depth-1 downto 0);`
56			`signal Data_Amount : integer range 0 to depth-1;`
57
58
59			`begin -- inout_mux`
60
61			`-- Continuous assignments`
62			`-- Assigns register values to outputs`
63			`Full <= Full_reg;`
64			`Empty <= Empty_reg;`
65			`One_Data_Left <= One_Data_Left_reg;`
66			`One_Place_Left <= One_Place_Left_reg;`
67			`Data_Out <= Fifo_Buffer (out_ptr);`
68			`-- Note! There is some old value in data output when fifo is empty.`
69
70
71			`Main : process (Clk, Rst_n)`
72			`begin -- process Main`
73			`if Rst_n = '0' then -- asynchronous reset (active low)`
74
75			`-- Reset all registers`
76			`-- Fifo is empty at first`
77			`Full_reg <= '0';`
78			`Empty_reg <= '1';`
79			`One_Data_Left_reg <= '0';`
80			`in_ptr <= 0;`
81			`out_ptr <= 0;`
82			`Data_Amount <= 0; --(others => '0');`
83
84			`if depth =1 then -- 30.07`
85			`One_Place_Left_reg <= '1';`
86			`else`
87			`One_Place_Left_reg <= '0';`
88			`end if;`
89
90			`for i in 0 to depth-1 loop`
91			`Fifo_Buffer (i) <= (others => '0');`
92			`end loop; -- i`
93
94			`elsif Clk'event and Clk = '1' then -- rising clock edge`
95
96
97			`-- 1) Write data to fifo`
98			`if Write_Enable = '1' and Read_Enable = '0' then`
99
100			`if Full_reg = '0' then`
101			`Empty_reg <= '0';`
102			`if (in_ptr = (depth-1)) then`
103			`in_ptr <= 0;`
104			`else`
105			`in_ptr <= in_ptr + 1;`
106			`end if;`
107			`out_ptr <= out_ptr;`
108			`Data_Amount <= Data_Amount +1;`
109			`Fifo_Buffer <= Fifo_Buffer; --02.06`
110			`Fifo_Buffer (in_ptr) <= Data_In;`
111
112			`-- Check if the fifo is getting full`
113			`if Data_Amount + 2 = depth then`
114			`Full_reg <= '0';`
115			`One_Place_Left_reg <= '1';`
116			`elsif Data_Amount +1 = depth then`
117			`Full_reg <= '1';`
118			`One_Place_Left_reg <= '0';`
119			`else`
120			`Full_reg <= '0';`
121			`One_Place_Left_reg <= '0';`
122			`end if;`
123
124			`-- If fifo was empty, it has now one data`
125			`if Empty_reg = '1' then`
126			`One_Data_Left_reg <= '1';`
127			`else`
128			`One_Data_Left_reg <= '0';`
129			`end if;`
130
131			`else`
132			`in_ptr <= in_ptr;`
133			`out_ptr <= out_ptr;`
134			`Full_reg <= Full_reg;`
135			`Empty_reg <= Empty_reg;`
136			`Fifo_Buffer <= Fifo_Buffer;`
137			`Data_Amount <= Data_Amount;`
138			`One_Data_Left_reg <= One_Data_Left_reg;`
139			`One_Place_Left_reg <= One_Place_Left_reg;`
140			`end if;`
141
142
143			`-- 2) Read data from fifo`
144			`elsif Write_Enable = '0' and Read_Enable = '1' then`
145
146			`if Empty_reg = '0' then`
147			`in_ptr <= in_ptr;`
148			`if (out_ptr = (depth-1)) then`
149			`out_ptr <= 0;`
150			`else`
151			`out_ptr <= out_ptr + 1;`
152			`end if;`
153			`Full_reg <= '0';`
154			`Data_Amount <= Data_Amount -1;`
155			`Fifo_Buffer <= Fifo_Buffer; --02.06`
156
157			`-- Debug`
158			`-- Fifo_Buffer (out_ptr) <= (others => '1');`
159
160			`-- Check if the fifo is getting empty`
161			`if Data_Amount = 2 then`
162			`Empty_reg <= '0';`
163			`One_data_Left_reg <= '1';`
164			`elsif Data_Amount = 1 then`
165			`Empty_reg <= '1';`
166			`One_Data_Left_reg <= '0';`
167			`else`
168			`Empty_reg <= '0';`
169			`One_Data_Left_reg <= '0';`
170			`end if;`
171
172			`-- If fifo was full, it is no more`
173			`if Full_reg = '1' then`
174			`One_Place_Left_reg <= '1';`
175			`else`
176			`One_Place_Left_reg <= '0';`
177			`end if;`
178
179			`else`
180			`in_ptr <= in_ptr;`
181			`out_ptr <= out_ptr;`
182			`Full_reg <= Full_reg;`
183			`Empty_reg <= Empty_reg;`
184			`Fifo_Buffer <= Fifo_Buffer;`
185			`Data_Amount <= Data_Amount;`
186			`One_Data_Left_reg <= One_Data_Left_reg;`
187			`One_Place_Left_reg <= One_Place_Left_reg;`
188			`end if;`
189
190
191			`-- 3) Write and read at the same time`
192			`elsif Write_Enable = '1' and Read_Enable = '1' then`
193
194
195			`if Full_reg = '0' and Empty_reg = '0' then`
196			`if (in_ptr = (depth-1)) then`
197			`in_ptr <= 0;`
198			`else`
199			`in_ptr <= in_ptr + 1;`
200			`end if;`
201			`if (out_ptr = (depth-1)) then`
202			`out_ptr <= 0;`
203			`else`
204			`out_ptr <= out_ptr + 1;`
205			`end if;`
206			`Full_reg <= '0';`
207			`Empty_reg <= '0';`
208			`Data_Amount <= Data_Amount;`
209			`One_Data_Left_reg <= One_Data_Left_reg;`
210			`One_Place_Left_reg <= One_Place_Left_reg;`
211
212			`Fifo_Buffer <= Fifo_Buffer; --02.06`
213			`Fifo_Buffer (in_ptr) <= Data_In;`
214			`-- Fifo_Buffer (out_ptr) <= (others => '1'); --debug`
215
216
217			`elsif Full_reg = '1' and Empty_reg = '0' then`
218			`-- Fifo is full, only reading is possible`
219			`in_ptr <= in_ptr;`
220			`if (out_ptr = (depth-1)) then`
221			`out_ptr <= 0;`
222			`else`
223			`out_ptr <= out_ptr + 1;`
224			`end if;`
225			`Full_reg <= '0';`
226			`One_Place_Left_reg <= '1';`
227			`Fifo_Buffer <= Fifo_Buffer; --02.06`
228			`--Fifo_Buffer (out_ptr) <= (others => '1'); -- Debug`
229			`Data_Amount <= Data_Amount -1;`
230
231			`-- Check if the fifo is getting empty`
232			`if Data_Amount = 2 then`
233			`Empty_reg <= '0';`
234			`One_data_Left_reg <= '1';`
235			`elsif Data_Amount = 1 then`
236			`Empty_reg <= '1';`
237			`One_Data_Left_reg <= '0';`
238			`else`
239			`Empty_reg <= '0';`
240			`One_Data_Left_reg <= '0';`
241			`end if;`
242
243
244			`elsif Full_reg = '0' and Empty_reg = '1' then`
245			`-- Fifo is empty, only writing is possible`
246			`if (in_ptr = (depth-1)) then`
247			`in_ptr <= 0;`
248			`else`
249			`in_ptr <= in_ptr + 1;`
250			`end if;`
251			`out_ptr <= out_ptr;`
252			`Empty_reg <= '0';`
253			`One_Data_Left_reg <= '1';`
254			`Fifo_Buffer <= Fifo_Buffer; --02.06`
255			`Fifo_Buffer (in_ptr) <= Data_In;`
256			`Data_Amount <= Data_Amount +1;`
257
258			`-- Check if the fifo is getting full`
259			`if Data_Amount + 2 = depth then`
260			`Full_reg <= '0';`
261			`One_Place_Left_reg <= '1';`
262			`elsif Data_Amount +1 = depth then`
263			`Full_reg <= '1';`
264			`One_Place_Left_reg <= '0';`
265			`else`
266			`Full_reg <= '0';`
267			`One_Place_Left_reg <= '0';`
268			`end if;`
269
270
271			`-- 4) Do nothing, fifo remains idle`
272			`else`
273
274			`in_ptr <= in_ptr;`
275			`out_ptr <= out_ptr;`
276			`Full_reg <= Full_reg;`
277			`Empty_reg <= Empty_reg;`
278			`Fifo_Buffer <= Fifo_Buffer;`
279			`Data_Amount <= Data_Amount;`
280			`One_Data_Left_reg <= One_Data_Left_reg;`
281			`One_Place_Left_reg <= One_Place_Left_reg;`
282			`end if;`
283
284			`else`
285			`-- Fifo is idle`
286			`in_ptr <= in_ptr;`
287			`out_ptr <= out_ptr;`
288			`Full_reg <= Full_reg;`
289			`Empty_reg <= Empty_reg;`
290			`Fifo_Buffer <= Fifo_Buffer;`
291			`Data_Amount <= Data_Amount;`
292			`One_Data_Left_reg <= One_Data_Left_reg;`
293			`One_Place_Left_reg <= One_Place_Left_reg;`
294			`end if;`
295
296			`end if;`
297			`end process Main;`
298
299			`end inout_mux;`