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-------------------------------------------------------------------------------
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-- Title : fifo
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-- Project :
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-------------------------------------------------------------------------------
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-- File : fifo_ram_dynamic.vhd
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-- Author :
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-- Company :
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-- Created : 2005-05-26
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-- Last update: 2006-03-02
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-- Platform :
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-- Standard : VHDL'87
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-------------------------------------------------------------------------------
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-- Description: Fifo w/dynamic depth implemented with dual port RAM
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-------------------------------------------------------------------------------
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-- Copyright (c) 2005
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2005-05-26 1.0 penttin5 Created
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-------------------------------------------------------------------------------
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--
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-- NOTE! generic depth_g is the maximum depth of fifo
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-- NOTE! Precision RTL synthesisis 2004c.45 doesn't infer the RAM with
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-- asynchronous read for Stratix 1 S40F780C5.
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-- Quartus II 4.2 infers RAM with asynchronic read but gives old RAM
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-- value when reading and writing simultaneusly to/from same address.
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-- That doesn't matter because FIFO doesn't read and write in the same
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-- address at the same time.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity fifo is
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generic (
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data_width_g : integer := 32;
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depth_g : integer := 10 -- this is the maximum depth of fifo!
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);
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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data_in : in std_logic_vector (data_width_g-1 downto 0);
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we_in : in std_logic;
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one_p_out : out std_logic;
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full_out : out std_logic;
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data_out : out std_logic_vector (data_width_g-1 downto 0);
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re_in : in std_logic;
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empty_out : out std_logic;
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one_d_out : out std_logic
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);
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end fifo;
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architecture rtl of fifo is
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-- this is the configuration RAM which holds the
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-- dynamic depth value at address 0
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component conf_ram
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port (
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address : in std_logic_vector(3 downto 0);
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clock : in std_logic;
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q : out std_logic_vector(7 downto 0)
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);
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end component;
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component dual_ram_async_read
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generic (
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ram_width : integer := 0;
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ram_depth : integer := 0);
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port
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(
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clock1 : in std_logic;
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clock2 : in std_logic;
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data : in std_logic_vector(0 to ram_width - 1);
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write_address : in integer range 0 to ram_depth - 1;
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read_address : in integer range 0 to ram_depth - 1;
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we : in std_logic;
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q : out std_logic_vector(0 to ram_width - 1)
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);
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end component; -- dual_ram_async_read
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signal write_address_r : integer range 0 to depth_g - 1;
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signal read_address_r : integer range 0 to depth_g - 1;
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signal write_read_count_r : integer range 0 to depth_g;
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signal ram_data_out_i : std_logic_vector(0 to data_width_g - 1);
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signal we_ram : std_logic;
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signal conf_ram_addr : std_logic_vector(3 downto 0);
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signal depth_from_conf_ram : std_logic_vector(7 downto 0);
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signal dynamic_depth_r : integer range 0 to depth_g;
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signal full_out_r : std_logic;
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begin -- rtl
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conf_ram_inst : conf_ram
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port map (
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address => (others => '0'),
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clock => clk,
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q => depth_from_conf_ram
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);
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gen_dual_ram : dual_ram_async_read
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generic map (
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ram_width => data_width_g,
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ram_depth => depth_g
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)
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port map (
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clock1 => clk,
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clock2 => clk,
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data => data_in,
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write_address => write_address_r,
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read_address => read_address_r,
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we => we_ram,
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q => ram_data_out_i
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);
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full_out <= full_out_r;
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-- write to fifo when write enabled and fifo not full
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we_ram <= we_in when full_out_r = '0'--write_read_count_r < dynamic_depth_r
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else '0';
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data_out <= ram_data_out_i;
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-- one_d_out <= '1' when write_read_count_r = 1 else
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-- '0';
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-- one_p_out <= '1' when write_read_count_r = dynamic_depth_r - 1 else
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-- '0';
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-- empty_out <= '1' when write_read_count_r = 0 else
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-- '0';
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-- full_out <= '1' when write_read_count_r >= dynamic_depth_r else
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-- '0';
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update_flags: process (clk, rst_n)
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begin -- process update_flags
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if rst_n = '0' then -- asynchronous reset (active low)
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one_d_out <= '0';
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one_p_out <= '0';
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empty_out <= '1';
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full_out_r <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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if (we_in = '0' and re_in = '0' and write_read_count_r = 1) or
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(we_in = '1' and re_in = '1' and write_read_count_r = 1) or
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(we_in = '1' and re_in = '0' and write_read_count_r = 0) or
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(we_in = '0' and re_in = '1' and write_read_count_r = 2) then
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one_d_out <= '1';
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else
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one_d_out <= '0';
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end if;
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if (we_in = '0' and re_in = '0' and write_read_count_r = dynamic_depth_r - 1) or
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(we_in = '1' and re_in = '1' and write_read_count_r = dynamic_depth_r - 1) or
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(we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r - 2) or
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(we_in = '0' and re_in = '1' and write_read_count_r = dynamic_depth_r) then
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one_p_out <= '1';
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else
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one_p_out <= '0';
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end if;
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if (we_in = '0' and re_in = '0' and write_read_count_r = 0) or
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(we_in = '0' and re_in = '1' and write_read_count_r = 0) or
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(we_in = '0' and re_in = '1' and write_read_count_r = 1) then
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empty_out <= '1';
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else
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empty_out <= '0';
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end if;
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if (we_in = '0' and re_in = '0' and write_read_count_r = dynamic_depth_r) or
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(we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r) or
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(we_in = '1' and re_in = '0' and write_read_count_r = dynamic_depth_r - 1) or
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(write_read_count_r > dynamic_depth_r) then
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full_out_r <= '1';
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else
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full_out_r <= '0';
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end if;
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end if;
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end process update_flags;
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-----------------------------------------------------------------------------
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-- Update dynamic depth
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-----------------------------------------------------------------------------
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update_dynamic_depth_r : process (clk, rst_n)
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begin -- process update_dynamic_depth_r
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if rst_n = '0' then -- asynchronous reset (active low)
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dynamic_depth_r <= depth_g;
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conf_ram_addr <= (others => '0');
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elsif clk'event and clk = '1' then -- rising clock edge
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conf_ram_addr <= (others => '0');
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if conv_integer(depth_from_conf_ram) > depth_g
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or depth_from_conf_ram =
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-- dynamic depth is bigger than maximum depth or
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-- it's not defined(zero) => Use the maximum depth
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conv_std_logic_vector(0, depth_from_conf_ram'length) then
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dynamic_depth_r <= depth_g;
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else
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-- update dynamic depth
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dynamic_depth_r <=
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conv_integer(depth_from_conf_ram);
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end if;
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end if;
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end process update_dynamic_depth_r;
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-----------------------------------------------------------------------------
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-- Update read and write addresses
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-----------------------------------------------------------------------------
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fifo_read_and_write : process (clk, rst_n)
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begin -- process fifo_read_and_write
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if rst_n = '0' then -- asynchronous reset (active low)
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write_read_count_r <= 0;
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read_address_r <= 0;
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write_address_r <= 0;
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elsif clk'event and clk = '1' then -- rising clock edge
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-- read if re_in = '1' and fifo not empty or
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-- simultaneus read and write and fifo full
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if re_in = '1' and ((we_in = '0' and write_read_count_r /= 0)
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or (we_in = '1'
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and write_read_count_r = dynamic_depth_r)) then
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write_read_count_r <= write_read_count_r - 1;
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if read_address_r = dynamic_depth_r - 1 then
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read_address_r <= 0;
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else
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read_address_r <= read_address_r + 1;
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end if;
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write_address_r <= write_address_r;
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-- write if we_in = '1' and fifo not full or
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-- simultaneus read and write and fifo empty
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elsif we_in = '1' and ((re_in = '0' and
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write_read_count_r /= dynamic_depth_r)
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or (re_in = '1' and write_read_count_r = 0)) then
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write_read_count_r <= write_read_count_r + 1;
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read_address_r <= read_address_r;
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if write_address_r = dynamic_depth_r - 1 then
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write_address_r <= 0;
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else
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write_address_r <= write_address_r + 1;
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end if;
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-- write and read at the same time if re_in = '1' and we_in = '1' and
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-- fifo not empty or full
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elsif re_in = '1' and we_in = '1'
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and write_read_count_r /= dynamic_depth_r
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and write_read_count_r /= 0 then
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write_read_count_r <= write_read_count_r;
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if read_address_r = dynamic_depth_r - 1 then
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read_address_r <= 0;
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else
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read_address_r <= read_address_r + 1;
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end if;
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if write_address_r = dynamic_depth_r - 1 then
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write_address_r <= 0;
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else
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write_address_r <= write_address_r + 1;
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end if;
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else
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write_read_count_r <= write_read_count_r;
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read_address_r <= read_address_r;
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write_address_r <= write_address_r;
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end if;
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end if;
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end process fifo_read_and_write;
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end rtl;
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