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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.storage/] [sdram2hibi/] [1.0/] [sim/] [create_makefile] - Blame information for rev 145

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1 145 lanttu
#
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# Skripti kaantaa kaikki vhdl-tiedostot ja tekee niista makefilen
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# Ymparistomuuttjat
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#       MEM_DATA_DIR    kertoo mihin hakemistoon kaannetyt fiilut laitetaan.
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#       MEM_WORK_DIR    kertoo minkä hakemiston alta lähdekoodit haetaan
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#
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clear
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# Omia VHDL-koodeja varten
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#Poistetaan vanha codelib ja tehdaan ja mapataan uusi
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echo "\nRemoving old vhdl library \n"
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rm -rf $MEM_DATA_DIR/codelib
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echo; echo "\nCreating a new library at"
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echo $MEM_DATA_DIR; echo
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mkdir $MEM_DATA_DIR
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vlib $MEM_DATA_DIR/codelib
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vmap work $MEM_DATA_DIR/codelib
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# Alteran solukirjastojen simulointimallit
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#vlib $MEM_DATA_DIR/altera_mf
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#vlib $MEM_DATA_DIR/lpm
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#vlib $MEM_DATA_DIR/stratix
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vlib $MEM_DATA_DIR/altera_vhdl_support
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vmap altera_vhdl_support $MEM_DATA_DIR/altera_vhdl_support
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vcom -work altera_vhdl_support ../Vhdl/altera_vhdl_support.vhd
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#vmap altera_mf $MEM_DATA_DIR/altera_mf
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#vmap lpm $MEM_DATA_DIR/lpm
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#vmap stratix $MEM_DATA_DIR/stratix
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#vcom -work lpm ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/220pack.vhd
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#vcom -work lpm ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/220model.vhd
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#vcom -work stratix ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/stratix_atoms.vhd
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#vcom -work stratix ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/stratix_components.vhd
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#vcom -work ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/altera_mf_components.vhd
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#vcom -work ../../Interconnections/Hibi/Hibi_v2/TryOutCodes/sim_lib/altera_mf.vhd
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# Hibi-koodit v2
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echo; echo "\nCompiling vhdl codes\n"; echo
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vcom -cover bcest ../Fifos/fifo.vhdl
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vcom -cover bcest ../Vhdl/sram_scalable_v2.vhdl
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vcom -cover bcest ../Vhdl/sdram50Mhz_cas3.vhd
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vcom -cover bcest ../Vhdl/sdram_ctrl.vhdl
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# Testipenkit
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echo; echo "\nCompiling vhdl testbenches\n";echo
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vcom -cover bcest ../Testbench/tb_sram_scalable.vhdl
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vcom -cover bcest ../Testbench/sdram_test_component.vhd
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vcom../Testbench/tb_sdram_ctrl.vhdl
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vcom ../Testbench/tb_sdramctrl_sdram50mhz.vhdl
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vcom ../Testbench/tb_sdram_test_component.vhdl
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echo;echo "\nCreating a new makefile"
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rm -f $MEM_WORK_DIR/makefile
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vmake $MEM_DATA_DIR/codelib > $MEM_WORK_DIR/makefile
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echo " --------Create_Makefile done------------- \n"
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