URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [altera_de_II_demo/] [1.0/] [ip_xact/] [altera_de_II_demo.1.0.xml] - Blame information for rev 145

Go to most recent revision | Details | Compare with Previous | View Log





        TUT
        soc
        altera_de_II_demo
        1.0
        Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker.
Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board. Note that sig_gen detects rising_edges of switch[17].
Switch[0] is reset.
 
DEMO INSTRUCTIONS.
1. Open altera_de_II_demo design in Kactus2
2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon
3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element.
4. Open generated project with Quartus. Compile and synthesize.
5. Program the FPGA.
        
                
                        clk
                        clk input
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        port_out
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                port_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        active low reset in
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        toggle_in
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                toggle_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                kactusHierarchical
                                
                                
                                
                                        structural_vhdl
                                
                        
                        
                                structural_vhdl
                                VHDL::
                                vhdl
                                altera_de_II_demo(top_level)
                                
                                        vhdlSource
                                
                        
                
                
                        
                                clk
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                        
                        
                                port_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                        
                        
                                rst_n
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                        
                        
                                toggle_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                        
                
        
        
                
                        vhdlSource
                        sourceFiles
                        
                                ../vhd/altera_de_II_demo.vhd
                                vhdlSource
                                true
                                soc
                                
                                        vcom
                                        -quiet -check_synthesis -work work
                                        true
                                
                        
                
                
                        quartusFiles
                        
                                ../quartus/atom_netlists/altera_de_II_demo.qsf
                                quartusPinmap
                                false
                                
                                        false
                                
                                Pinmap file for Altera DE2 development board. Quartus generator will use this as a template (practically, it copies all the data and updates the file paths).
                        
                
                
                        Documentation
                        Detailed instructions how to repeat the demo.
                        
                                ../doc/Altera DE 2 demo instructions for Kactus 2.pptx
                                documentation
                                false
                                
                                        false
                                
                                Step-by-step instructions how to generate top-level VHDL and Quartus project for this demo SoC
                        
                
                
                        ModelsimScripts
                        simulation
                        
                                ../sim/sim.do
                                Modelsim do-file
                                false
                                
                                        false
                                
                        
                        
                                ../sim/all_waves.do
                                Modelsim do-file
                                false
                                
                                        false
                                
                        
                        
                                ../sim/compile_all.do
                                ModelsimScript
                                false
                                Script file for Modelsim that compiles all files for view kactusHierarchical.
                        
                
        
        
                
                        
                                SoC
                                HW
                                Mutable
                        
                
        


Browse

Tools

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [altera_de_II_demo/] [1.0/] [ip_xact/] [altera_de_II_demo.1.0.xml] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu
2
3
4			`TUT`
5			`soc`
6			`altera_de_II_demo`
7			`1.0`
8			`Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker.`
9			`Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board. Note that sig_gen detects rising_edges of switch[17].`
10			`Switch[0] is reset.`
11
12			`DEMO INSTRUCTIONS.`
13			`1. Open altera_de_II_demo design in Kactus2`
14			`2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon`
15			`3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element.`
16			`4. Open generated project with Quartus. Compile and synthesize.`
17			`5. Program the FPGA.`
18
19
20			`clk`
21			`clk input`
22
23
24
25			`false`
26
27
28
29			`CLK`
30
31			`0`
32			`0`
33
34
35
36			`clk`
37
38			`0`
39			`0`
40
41
42
43
44			`8`
45			`little`
46
47
48			`port_out`
49
50
51
52			`false`
53
54
55
56			`gpio`
57
58			`0`
59			`0`
60
61
62
63			`port_out`
64
65			`0`
66			`0`
67
68
69
70
71			`8`
72			`little`
73
74
75			`rst_n`
76			`active low reset in`
77
78
79
80			`false`
81
82
83
84			`RESETn`
85
86			`0`
87			`0`
88
89
90
91			`rst_n`
92
93			`0`
94			`0`
95
96
97
98
99			`8`
100			`little`
101
102
103			`toggle_in`
104
105
106
107			`false`
108
109
110
111			`gpio`
112
113			`0`
114			`0`
115
116
117
118			`toggle_in`
119
120			`0`
121			`0`
122
123
124
125
126			`8`
127			`little`
128
129
130
131
132
133			`kactusHierarchical`
134
135
136
137			`structural_vhdl`
138
139
140
141			`structural_vhdl`
142			`VHDL::`
143			`vhdl`
144			`altera_de_II_demo(top_level)`
145
146			`vhdlSource`
147
148
149
150
151
152			`clk`
153
154			`in`
155
156			`0`
157			`0`
158
159
160
161			`std_logic`
162			`IEEE.std_logic_1164.all`
163			`kactusHierarchical_rtl`
164			`rtl`
165			`kactusHierarchical`
166			`structural_vhdl`
167
168
169
170
171
172			`port_out`
173
174			`out`
175
176			`0`
177			`0`
178
179
180
181			`std_logic`
182			`IEEE.std_logic_1164.all`
183			`kactusHierarchical_rtl`
184			`rtl`
185			`kactusHierarchical`
186			`structural_vhdl`
187
188
189
190
191
192			`rst_n`
193
194			`in`
195
196			`0`
197			`0`
198
199
200
201			`std_logic`
202			`IEEE.std_logic_1164.all`
203			`kactusHierarchical_rtl`
204			`rtl`
205			`kactusHierarchical`
206			`structural_vhdl`
207
208
209
210
211
212			`toggle_in`
213
214			`in`
215
216			`0`
217			`0`
218
219
220
221			`std_logic`
222			`IEEE.std_logic_1164.all`
223			`kactusHierarchical_rtl`
224			`rtl`
225			`kactusHierarchical`
226			`structural_vhdl`
227
228
229
230
231
232
233
234
235			`vhdlSource`
236			`sourceFiles`
237
238			`../vhd/altera_de_II_demo.vhd`
239			`vhdlSource`
240			`true`
241			`soc`
242
243			`vcom`
244			`-quiet -check_synthesis -work work`
245			`true`
246
247
248
249
250			`quartusFiles`
251
252			`../quartus/atom_netlists/altera_de_II_demo.qsf`
253			`quartusPinmap`
254			`false`
255
256			`false`
257
258			`Pinmap file for Altera DE2 development board. Quartus generator will use this as a template (practically, it copies all the data and updates the file paths).`
259
260
261
262			`Documentation`
263			`Detailed instructions how to repeat the demo.`
264
265			`../doc/Altera DE 2 demo instructions for Kactus 2.pptx`
266			`documentation`
267			`false`
268
269			`false`
270
271			`Step-by-step instructions how to generate top-level VHDL and Quartus project for this demo SoC`
272
273
274
275			`ModelsimScripts`
276			`simulation`
277
278			`../sim/sim.do`
279			`Modelsim do-file`
280			`false`
281
282			`false`
283
284
285
286			`../sim/all_waves.do`
287			`Modelsim do-file`
288			`false`
289
290			`false`
291
292
293
294			`../sim/compile_all.do`
295			`ModelsimScript`
296			`false`
297			`Script file for Modelsim that compiles all files for view kactusHierarchical.`
298
299
300
301
302
303
304			`SoC`
305			`HW`
306			`Mutable`
307
308
309
310