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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [altera_de_II_demo/] [1.0/] [ip_xact/] [altera_de_II_demo.1.0.xml] - Blame information for rev 148

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        TUT
        soc
        altera_de_II_demo
        1.0
        Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker.
Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board. Note that sig_gen detects rising_edges of switch[17].
Switch[0] is reset.
 
DEMO INSTRUCTIONS.
1. Open altera_de_II_demo design in Kactus2
2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon
3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element.
4. Open generated project with Quartus. Compile and synthesize.
5. Program the FPGA.
        
                
                        clk
                        clk input
                        
                        
                        
                        false
                        
                                
                                        
                                                CLK
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                clk
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        port_out
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                port_out
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        rst_n
                        active low reset in
                        
                        
                        
                        false
                        
                                
                                        
                                                RESETn
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                rst_n
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
                
                        toggle_in
                        
                        
                        
                        false
                        
                                
                                        
                                                gpio
                                                
                                                        0
                                                        0
                                                
                                        
                                        
                                                toggle_in
                                                
                                                        0
                                                        0
                                                
                                        
                                
                        
                        8
                        little
                
        
        
                
                        
                                kactusHierarchical
                                
                                
                                
                                        structural_vhdl
                                
                        
                        
                                structural_vhdl
                                VHDL::
                                vhdl
                                altera_de_II_demo(top_level)
                                
                                        vhdlSource
                                
                        
                
                
                        
                                clk
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        foobar
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                                
                        
                        
                                port_out
                                
                                        out
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        foobar
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                                
                        
                        
                                rst_n
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        foobar
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                                
                        
                        
                                toggle_in
                                
                                        in
                                        
                                                0
                                                0
                                        
                                        
                                                
                                                        std_logic
                                                        IEEE.std_logic_1164.all
                                                        kactusHierarchical_rtl
                                                        rtl
                                                        foobar
                                                        kactusHierarchical
                                                        structural_vhdl
                                                
                                        
                                
                                
                        
                
        
        
                
                        vhdlSource
                        sourceFiles
                        
                                ../vhd/altera_de_II_demo.vhd
                                vhdlSource
                                true
                                soc
                                
                                        vcom
                                        -quiet -check_synthesis -work work
                                        true
                                
                        
                
                
                        quartusFiles
                        
                                ../quartus/atom_netlists/altera_de_II_demo.qsf
                                quartusPinmap
                                false
                                Pinmap file for Altera DE2 development board. Quartus generator will use this as a template (practically, it copies all the data and updates the file paths).
                        
                
                
                        Documentation
                        Detailed instructions how to repeat the demo.
                        
                                ../doc/Altera DE 2 demo instructions for Kactus 2.pptx
                                documentation
                                false
                                Step-by-step instructions how to generate top-level VHDL and Quartus project for this demo SoC
                        
                
                
                        ModelsimScripts
                        simulation
                        
                                ../sim/sim.do
                                Modelsim do-file
                                false
                        
                        
                                ../sim/all_waves.do
                                Modelsim do-file
                                false
                        
                        
                                ../sim/compile_all.do
                                ModelsimScript
                                false
                                Script file for Modelsim that compiles all files for view kactusHierarchical.
                        
                
        
        
                
                        
                                SoC
                                HW
                                Mutable
                        
                
        


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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [altera_de_II_demo/] [1.0/] [ip_xact/] [altera_de_II_demo.1.0.xml] - Blame information for rev 148

Line No.	Rev	Author	Line
1	145	lanttu
2	147	lanttu
3
4	148	lanttu
5
6	145	lanttu
7			`TUT`
8			`soc`
9			`altera_de_II_demo`
10			`1.0`
11			`Simple demo for Altera DE2 development board.Instantietes two components sig_gen and port blinker.`
12			`Sig_gen reads switch[17] from DE2 board and activates port blinker to blink leds in DE2 Board. Note that sig_gen detects rising_edges of switch[17].`
13			`Switch[0] is reset.`
14
15			`DEMO INSTRUCTIONS.`
16			`1. Open altera_de_II_demo design in Kactus2`
17			`2. Generate top-level VHDL with Kactus2 vhdl generator the ribbon`
18			`3. Generate Qurtus project for synthesizing demo design by clicking Quartus project generator in the ribbon element.`
19			`4. Open generated project with Quartus. Compile and synthesize.`
20			`5. Program the FPGA.`
21
22
23			`clk`
24			`clk input`
25
26
27
28			`false`
29
30
31
32			`CLK`
33
34			`0`
35			`0`
36
37
38
39			`clk`
40
41			`0`
42			`0`
43
44
45
46
47			`8`
48			`little`
49
50
51			`port_out`
52
53
54
55			`false`
56
57
58
59			`gpio`
60
61			`0`
62			`0`
63
64
65
66			`port_out`
67
68			`0`
69			`0`
70
71
72
73
74			`8`
75			`little`
76
77
78			`rst_n`
79			`active low reset in`
80
81
82
83			`false`
84
85
86
87			`RESETn`
88
89			`0`
90			`0`
91
92
93
94			`rst_n`
95
96			`0`
97			`0`
98
99
100
101
102			`8`
103			`little`
104
105
106			`toggle_in`
107
108
109
110			`false`
111
112
113
114			`gpio`
115
116			`0`
117			`0`
118
119
120
121			`toggle_in`
122
123			`0`
124			`0`
125
126
127
128
129			`8`
130			`little`
131
132
133
134
135
136			`kactusHierarchical`
137
138
139
140			`structural_vhdl`
141
142
143
144			`structural_vhdl`
145			`VHDL::`
146			`vhdl`
147			`altera_de_II_demo(top_level)`
148
149			`vhdlSource`
150
151
152
153
154
155			`clk`
156
157			`in`
158
159			`0`
160			`0`
161
162
163
164			`std_logic`
165			`IEEE.std_logic_1164.all`
166			`kactusHierarchical_rtl`
167			`rtl`
168	148	lanttu	`foobar`
169	145	lanttu	`kactusHierarchical`
170			`structural_vhdl`
171
172
173
174	147	lanttu
175	145	lanttu
176
177			`port_out`
178
179			`out`
180
181			`0`
182			`0`
183
184
185
186			`std_logic`
187			`IEEE.std_logic_1164.all`
188			`kactusHierarchical_rtl`
189			`rtl`
190	148	lanttu	`foobar`
191	145	lanttu	`kactusHierarchical`
192			`structural_vhdl`
193
194
195
196	147	lanttu
197	145	lanttu
198
199			`rst_n`
200
201			`in`
202
203			`0`
204			`0`
205
206
207
208			`std_logic`
209			`IEEE.std_logic_1164.all`
210			`kactusHierarchical_rtl`
211			`rtl`
212	148	lanttu	`foobar`
213	145	lanttu	`kactusHierarchical`
214			`structural_vhdl`
215
216
217
218	147	lanttu
219	145	lanttu
220
221			`toggle_in`
222
223			`in`
224
225			`0`
226			`0`
227
228
229
230			`std_logic`
231			`IEEE.std_logic_1164.all`
232			`kactusHierarchical_rtl`
233			`rtl`
234	148	lanttu	`foobar`
235	145	lanttu	`kactusHierarchical`
236			`structural_vhdl`
237
238
239
240	147	lanttu
241	145	lanttu
242
243
244
245
246			`vhdlSource`
247			`sourceFiles`
248
249			`../vhd/altera_de_II_demo.vhd`
250			`vhdlSource`
251			`true`
252			`soc`
253
254			`vcom`
255			`-quiet -check_synthesis -work work`
256			`true`
257
258
259
260
261			`quartusFiles`
262
263			`../quartus/atom_netlists/altera_de_II_demo.qsf`
264			`quartusPinmap`
265			`false`
266			`Pinmap file for Altera DE2 development board. Quartus generator will use this as a template (practically, it copies all the data and updates the file paths).`
267
268
269
270			`Documentation`
271			`Detailed instructions how to repeat the demo.`
272
273			`../doc/Altera DE 2 demo instructions for Kactus 2.pptx`
274			`documentation`
275			`false`
276			`Step-by-step instructions how to generate top-level VHDL and Quartus project for this demo SoC`
277
278
279
280			`ModelsimScripts`
281			`simulation`
282
283			`../sim/sim.do`
284			`Modelsim do-file`
285			`false`
286
287
288			`../sim/all_waves.do`
289			`Modelsim do-file`
290			`false`
291
292
293			`../sim/compile_all.do`
294			`ModelsimScript`
295			`false`
296			`Script file for Modelsim that compiles all files for view kactusHierarchical.`
297
298
299
300
301
302
303			`SoC`
304			`HW`
305			`Mutable`
306
307
308
309