URL
https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk
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lanttu |
# Script compiles all vhdl-files and generates a makefile for them
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# This script is tested for Modelsim version 6.6a
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.main clear
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echo " Generating libraries for files"
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echo "Processing component TUT:ip.hwp.accelerator:port_blinker:1.0"
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echo "Processing file set hdlSources of component TUT:ip.hwp.accelerator:port_blinker:1.0."
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echo " Adding library work"
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vlib work
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vcom -quiet -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.accelerator/port_blinker/1.0/vhd/port_blinker.vhd
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echo "Processing component TUT:ip.hwp.accelerator:sig_gen:1.0"
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echo "Processing file set hdlSources of component TUT:ip.hwp.accelerator:sig_gen:1.0."
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vcom -quiet -check_synthesis D:/user/ege/Svn/daci_ip/trunk/ip.hwp.accelerator/sig_gen/1.0/vhd/sig_gen.vhd
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echo "Processing component TUT:soc:altera_de_II_demo:1.0"
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echo "Processing file set vhdlSource of component TUT:soc:altera_de_II_demo:1.0."
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echo " Adding library soc"
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vlib soc
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vcom -quiet -check_synthesis -work work D:/user/ege/Svn/daci_ip/trunk/soc/altera_de_II_demo/1.0/vhd/altera_de_II_demo.vhd
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echo " Creating a new Makefile"
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# remove the old makefile
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rm -f Makefile
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vmake work > Makefile
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echo " Script has been executed "
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