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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [basic_tester_example/] [1.0/] [ip_xact/] [basic_tester_hibi_example.1.0.xml] - Blame information for rev 145

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        TUT
        soc
        basic_tester_hibi_example
        1.0
        Simple example on how to use basic_tester with hibi.
Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.
 
 Tx sends few words to rx which takes and checks them.
Basic_tester is meant for simulation only.
        
                
                        
                                structural_seg
                                Instantiates hibi as segement.
Graphical block diagram view. Hence, its type is "hierarchical".
                                ::
                                
                                
                                        structural_rtl
                                
                        
                        
                                structural_rtl
                                Auto-generated top-level from either of the block diagram views.
                                VHDL:Kactus2:
                                vhdl
                                basic_tester_hibi_example(structural)
                                
                                        structural_vhdlSource
                                
                        
                        
                                structural_wra
                                Instantiates hibi from the wrappers.
Graphical block diagram view. Hence, its type is "hierarchical".
                                
                                
                                
                                        structural_rtl
                                
                        
                
        
        
                
                        ModelsimScripts
                        simulation
                        
                                ../sim/basic_tester_hibi_example_waves.do
                                Modelsim script
                                false
                                Add necessary signals to wave window and formats them.
 
This works with both versions (seg and wra)
                        
                        
                                Modelsim script
                                say "do script_name.do" in Modelsim
                                none
                                false
                        
                
                
                        structural_vhdlSource
                        Auto-generated top-level VHDL
                        sourceFiles
                        
                                ../vhd/basic_tester_hibi_example.vhd
                                vhdlSource
                                true
                                work
                                
                                        vcom
                                        -quiet -check_synthesis -work work
                                        true
                                
                                Auto-generated by Kactus.
                        
                        
                                vhdlSource
                                vcom
                                -quiet -check_synthesis -work work
                                true
                        
                
        
        
                
                        
                                SoC
                                HW
                                Template
                        
                
        


Line No.	Rev	Author	Line
1	145	lanttu
2
3
4
5
6
7			`TUT`
8			`soc`
9			`basic_tester_hibi_example`
10			`1.0`
11			`Simple example on how to use basic_tester with hibi.`
12			`Hibi is instantiated a) as a segment, b) from 4 wrappers and an OR-network.`
13
14			`Tx sends few words to rx which takes and checks them.`
15			`Basic_tester is meant for simulation only.`
16
17
18
19			`structural_seg`
20			`Instantiates hibi as segement.`
21			`Graphical block diagram view. Hence, its type is "hierarchical".`
22			`::`
23
24
25			`structural_rtl`
26
27
28
29			`structural_rtl`
30			`Auto-generated top-level from either of the block diagram views.`
31			`VHDL:Kactus2:`
32			`vhdl`
33			`basic_tester_hibi_example(structural)`
34
35			`structural_vhdlSource`
36
37
38
39			`structural_wra`
40			`Instantiates hibi from the wrappers.`
41			`Graphical block diagram view. Hence, its type is "hierarchical".`
42
43
44
45			`structural_rtl`
46
47
48
49
50
51
52			`ModelsimScripts`
53			`simulation`
54
55			`../sim/basic_tester_hibi_example_waves.do`
56			`Modelsim script`
57			`false`
58			`Add necessary signals to wave window and formats them.`
59
60			`This works with both versions (seg and wra)`
61
62
63			`Modelsim script`
64			`say "do script_name.do" in Modelsim`
65			`none`
66			`false`
67
68
69
70			`structural_vhdlSource`
71			`Auto-generated top-level VHDL`
72			`sourceFiles`
73
74			`../vhd/basic_tester_hibi_example.vhd`
75			`vhdlSource`
76			`true`
77			`work`
78
79			`vcom`
80			`-quiet -check_synthesis -work work`
81			`true`
82
83			`Auto-generated by Kactus.`
84
85
86			`vhdlSource`
87			`vcom`
88			`-quiet -check_synthesis -work work`
89			`true`
90
91
92
93
94
95
96			`SoC`
97			`HW`
98			`Template`
99
100
101
102

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[/] [funbase_ip_library/] [trunk/] [TUT/] [soc/] [basic_tester_example/] [1.0/] [ip_xact/] [basic_tester_hibi_example.1.0.xml] - Blame information for rev 145